tile: BaseTile refactor, pt 2
* 2 layer cake * no more bundle traits, only call to IO
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@ -287,8 +287,7 @@ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(
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}
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/** Mix-ins for constructing tiles that might have a PTW */
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trait CanHavePTW extends HasHellaCache { this: BaseTile =>
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implicit val p: Parameters
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trait CanHavePTW extends HasTileParameters with HasHellaCache { this: BaseTile =>
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val module: CanHavePTWModule
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var nPTWPorts = 1
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nDCachePorts += usingPTW.toInt
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