riscv/rocket-chip
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tile: BaseTile refactor, pt 2

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* 2 layer cake
* no more bundle traits, only call to IO
This commit is contained in:
Henry Cook committed 2018-01-02 15:37:31 -08:00
1 parent 1579ddb97e
commit efe7165b54
12 files changed
+49 -93
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src/main/scala/rocket/Frontend.scala
-4
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@@ -315,10 +315,6 @@ trait HasICacheFrontend extends CanHavePTW { this: BaseTile =>
nPTWPorts += 1
}
trait HasICacheFrontendBundle {
val outer: HasICacheFrontend
}
trait HasICacheFrontendModule extends CanHavePTWModule {
val outer: HasICacheFrontend
ptwPorts += outer.frontend.module.io.ptw