riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

tile: BaseTile refactor, pt 2

Browse Source 
* 2 layer cake
* no more bundle traits, only call to IO
This commit is contained in:
Henry Cook
2018-01-02 15:37:31 -08:00
parent 1579ddb97e
commit efe7165b54
12 changed files with 49 additions and 93 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/main/scala/groundtest/Coreplex.scala
View File

@ -44,9 +44,9 @@ class GroundTestCoreplexModule[+L <: GroundTestCoreplex](_outer: L) extends Base
with HasMasterAXI4MemPortModuleImp {
val success = IO(Bool(OUTPUT))
outer.tiles.zipWithIndex.map { case(t, i) => t.module.io.hartid := UInt(i) }
outer.tiles.zipWithIndex.map { case(t, i) => t.module.constants.hartid := UInt(i) }
val status = DebugCombiner(outer.tiles.map(_.module.io.status))
val status = DebugCombiner(outer.tiles.map(_.module.status))
success := status.finished
}