tile: BaseTile refactor, pt 2

* 2 layer cake
* no more bundle traits, only call to IO

src/main/scala/groundtest/Coreplex.scala

@@ -44,9 +44,9 @@ class GroundTestCoreplexModule[+L <: GroundTestCoreplex](_outer: L) extends Base
     with HasMasterAXI4MemPortModuleImp {
   val success = IO(Bool(OUTPUT))
 
-  outer.tiles.zipWithIndex.map { case(t, i) => t.module.io.hartid := UInt(i) }
+  outer.tiles.zipWithIndex.map { case(t, i) => t.module.constants.hartid := UInt(i) }
 
-  val status = DebugCombiner(outer.tiles.map(_.module.io.status))
+  val status = DebugCombiner(outer.tiles.map(_.module.status))
   success := status.finished
 }
 

src/main/scala/groundtest/Tile.scala

@@ -39,15 +39,12 @@ abstract class GroundTestTile(params: GroundTestTileParams)
 
   val dcacheOpt = params.dcache.map { dc => LazyModule(new DCache(0)) }
 
-  override lazy val module = new GroundTestTileModule(this, () => new GroundTestTileBundle(this))
+  override lazy val module = new GroundTestTileModule(this)
 }
 
-class GroundTestTileBundle[+L <: GroundTestTile](_outer: L) extends BaseTileBundle(_outer) {
-  val status = new GroundTestStatus
+class GroundTestTileModule(outer: GroundTestTile) extends BaseTileModule(outer) {
+  val status = IO(new GroundTestStatus)
   val halt_and_catch_fire = None
-}
-
-class GroundTestTileModule[+L <: GroundTestTile, +B <: GroundTestTileBundle[L]](_outer: L, _io: () => B) extends BaseTileModule(_outer, _io) {
 
   outer.dcacheOpt foreach { dcache =>
     val ptw = Module(new DummyPTW(1))

src/main/scala/groundtest/TraceGen.scala

@@ -583,10 +583,10 @@ class TraceGenTile(val id: Int, val params: TraceGenParams)(implicit p: Paramete
   override lazy val module = new TraceGenTileModule(this)
 }
 
-class TraceGenTileModule(outer: TraceGenTile) extends GroundTestTileModule(outer, () => new GroundTestTileBundle(outer)) {
+class TraceGenTileModule(outer: TraceGenTile) extends GroundTestTileModule(outer) {
 
   val tracegen = Module(new TraceGenerator(outer.params))
-  tracegen.io.hartid := io.hartid
+  tracegen.io.hartid := constants.hartid
 
   outer.dcacheOpt foreach { dcache =>
     val dcacheIF = Module(new SimpleHellaCacheIF())
@@ -594,10 +594,10 @@ class TraceGenTileModule(outer: TraceGenTile) extends GroundTestTileModule(outer
     dcache.module.io.cpu <> dcacheIF.io.cache
   }
 
-  io.status.finished := tracegen.io.finished
-  io.status.timeout.valid := tracegen.io.timeout
-  io.status.timeout.bits := UInt(0)
-  io.status.error.valid := Bool(false)
+  status.finished := tracegen.io.finished
+  status.timeout.valid := tracegen.io.timeout
+  status.timeout.bits := UInt(0)
+  status.error.valid := Bool(false)
 
   assert(!tracegen.io.timeout, s"TraceGen tile ${outer.id}: request timed out")
 }