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tile: BaseTile refactor, pt 2

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* 2 layer cake
* no more bundle traits, only call to IO
This commit is contained in:
Henry Cook
2018-01-02 15:37:31 -08:00
parent 1579ddb97e
commit efe7165b54
12 changed files with 49 additions and 93 deletions
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6
src/main/scala/coreplex/HasTiles.scala
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@ -32,7 +32,7 @@ trait HasTilesModuleImp extends LazyModuleImp
def resetVectorBits: Int = {
// Consider using the minimum over all widths, rather than enforcing homogeneity
val vectors = outer.tiles.map(_.module.io.reset_vector)
val vectors = outer.tiles.map(_.module.constants.reset_vector)
require(vectors.tail.forall(_.getWidth == vectors.head.getWidth))
vectors.head.getWidth
}
@ -45,8 +45,8 @@ trait HasTilesModuleImp extends LazyModuleImp
outer.tiles.map(_.module).zip(tile_inputs).foreach { case(tile, wire) =>
tile.clock := wire.clock
tile.reset := wire.reset
tile.io.hartid := wire.hartid
tile.io.reset_vector := wire.reset_vector
tile.constants.hartid := wire.hartid
tile.constants.reset_vector := wire.reset_vector
}
}