Merge pull request #1098 from freechipsproject/frontend
Frontend improvements
This commit is contained in:
Andrew Waterman
GitHub
commit
efdb418559
@ -10,12 +10,18 @@ import freechips.rocketchip.coreplex.CacheBlockBytes
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import freechips.rocketchip.tile.HasCoreParameters
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import freechips.rocketchip.util._
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case class BHTParams(
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nEntries: Int = 512,
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counterLength: Int = 1,
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historyLength: Int = 8,
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historyBits: Int = 3)
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case class BTBParams(
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nEntries: Int = 30,
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nEntries: Int = 28,
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nMatchBits: Int = 14,
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nPages: Int = 6,
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nRAS: Int = 6,
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nBHT: Int = 256,
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bhtParams: Option[BHTParams] = Some(BHTParams()),
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updatesOutOfOrder: Boolean = false)
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trait HasBtbParameters extends HasCoreParameters {
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@ -51,9 +57,10 @@ class RAS(nras: Int) {
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}
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class BHTResp(implicit p: Parameters) extends BtbBundle()(p) {
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val history = UInt(width = log2Up(btbParams.nBHT).max(1))
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val value = UInt(width = 2)
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val taken = Bool()
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val history = UInt(width = btbParams.bhtParams.map(_.historyLength).getOrElse(1))
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val value = UInt(width = btbParams.bhtParams.map(_.counterLength).getOrElse(1))
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def taken = value(0)
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def strongly_taken = value === 1
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}
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// BHT contains table of 2-bit counters and a global history register.
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@ -65,32 +72,43 @@ class BHTResp(implicit p: Parameters) extends BtbBundle()(p) {
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// - each counter corresponds with the address of the fetch packet ("fetch pc").
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// - updated when a branch resolves (and BTB was a hit for that branch).
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// The updating branch must provide its "fetch pc".
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class BHT(nbht: Int)(implicit val p: Parameters) extends HasCoreParameters {
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val nbhtbits = log2Up(nbht)
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class BHT(params: BHTParams)(implicit val p: Parameters) extends HasCoreParameters {
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def index(addr: UInt, history: UInt) = {
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def hashHistory(hist: UInt) = if (params.historyLength == params.historyBits) hist else {
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val k = math.sqrt(3)/2
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val i = BigDecimal(k * math.pow(2, params.historyLength)).toBigInt
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(i.U * hist)(params.historyLength-1, params.historyLength-params.historyBits)
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}
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def hashAddr(addr: UInt) = {
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val hi = addr >> log2Ceil(fetchBytes)
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hi(log2Ceil(params.nEntries)-1, 0) ^ (hi >> log2Ceil(params.nEntries))(1, 0)
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}
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hashAddr(addr) ^ (hashHistory(history) << (log2Up(params.nEntries) - params.historyBits))
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}
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def get(addr: UInt): BHTResp = {
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val res = Wire(new BHTResp)
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val index = addr(nbhtbits+log2Up(coreInstBytes)-1, log2Up(coreInstBytes)) ^ history
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res.value := table(index)
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res.value := table(index(addr, history))
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res.history := history
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res.taken := res.value(0)
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res
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}
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def updateTable(addr: UInt, d: BHTResp, taken: Bool): Unit = {
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val index = addr(nbhtbits+log2Up(coreInstBytes)-1, log2Up(coreInstBytes)) ^ d.history
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table(index) := Cat(taken, (d.value(1) & d.value(0)) | ((d.value(1) | d.value(0)) & taken))
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table(index(addr, d.history)) := (params.counterLength match {
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case 1 => taken
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case 2 => Cat(taken ^ d.value(0), d.value === 1 || d.value(1) && taken)
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})
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}
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def resetHistory(d: BHTResp): Unit = {
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history := d.history
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}
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def updateHistory(addr: UInt, d: BHTResp, taken: Bool): Unit = {
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history := Cat(taken, d.history(nbhtbits-1,1))
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history := Cat(taken, d.history >> 1)
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}
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def advanceHistory(taken: Bool): Unit = {
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history := Cat(taken, history(nbhtbits-1,1))
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history := Cat(taken, history >> 1)
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}
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private val table = Mem(nbht, UInt(width = 2))
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val history = Reg(UInt(width = nbhtbits))
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private val table = Mem(params.nEntries, UInt(width = params.counterLength))
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val history = Reg(UInt(width = params.historyLength))
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}
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object CFIType {
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@ -106,7 +124,7 @@ object CFIType {
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// - "pc" is what future fetch PCs will tag match against.
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// - "br_pc" is the PC of the branch instruction.
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class BTBUpdate(implicit p: Parameters) extends BtbBundle()(p) {
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val prediction = Valid(new BTBResp)
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val prediction = new BTBResp
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val pc = UInt(width = vaddrBits)
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val target = UInt(width = vaddrBits)
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val taken = Bool()
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@ -118,8 +136,9 @@ class BTBUpdate(implicit p: Parameters) extends BtbBundle()(p) {
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// BHT update occurs during branch resolution on all conditional branches.
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// - "pc" is what future fetch PCs will tag match against.
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class BHTUpdate(implicit p: Parameters) extends BtbBundle()(p) {
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val prediction = Valid(new BTBResp)
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val prediction = new BHTResp
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val pc = UInt(width = vaddrBits)
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val branch = Bool()
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val taken = Bool()
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val mispredict = Bool()
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}
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@ -127,7 +146,6 @@ class BHTUpdate(implicit p: Parameters) extends BtbBundle()(p) {
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class RASUpdate(implicit p: Parameters) extends BtbBundle()(p) {
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val cfiType = CFIType()
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val returnAddr = UInt(width = vaddrBits)
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val prediction = Valid(new BTBResp)
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}
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// - "bridx" is the low-order PC bits of the predicted branch (after
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@ -161,6 +179,7 @@ class BTB(implicit p: Parameters) extends BtbModule {
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val bht_advance = Valid(new BTBResp).flip
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val ras_update = Valid(new RASUpdate).flip
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val ras_head = Valid(UInt(width = vaddrBits))
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val flush = Bool().asInput
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}
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val idxs = Reg(Vec(entries, UInt(width=matchBits - log2Up(coreInstBytes))))
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@ -195,7 +214,7 @@ class BTB(implicit p: Parameters) extends BtbModule {
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if (updatesOutOfOrder) {
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val updateHits = (pageHit << 1)(Mux1H(idxMatch(r_btb_update.bits.pc), idxPages))
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(updateHits.orR, OHToUInt(updateHits))
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} else (r_btb_update.bits.prediction.valid && r_btb_update.bits.prediction.bits.entry < entries, r_btb_update.bits.prediction.bits.entry)
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} else (r_btb_update.bits.prediction.entry < entries, r_btb_update.bits.prediction.entry)
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val useUpdatePageHit = updatePageHit.orR
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val usePageHit = pageHit.orR
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@ -218,9 +237,14 @@ class BTB(implicit p: Parameters) extends BtbModule {
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nextPageRepl := Mux(next >= nPages, next(0), next)
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}
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val repl = new PseudoLRU(entries)
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val waddr = Mux(updateHit, updateHitAddr, repl.replace)
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val r_resp = Pipe(io.resp)
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when (r_resp.valid && r_resp.bits.taken || r_btb_update.valid) {
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repl.access(Mux(r_btb_update.valid, waddr, r_resp.bits.entry))
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}
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when (r_btb_update.valid) {
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val nextRepl = Counter(r_btb_update.valid && !updateHit, entries)._1
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val waddr = Mux(updateHit, updateHitAddr, nextRepl)
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val mask = UIntToOH(waddr)
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idxs(waddr) := r_btb_update.bits.pc(matchBits-1, log2Up(coreInstBytes))
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tgts(waddr) := update_target(matchBits-1, log2Up(coreInstBytes))
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@ -257,24 +281,25 @@ class BTB(implicit p: Parameters) extends BtbModule {
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when (PopCountAtLeast(idxHit, 2)) {
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isValid := isValid & ~idxHit
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}
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when (io.flush) {
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isValid := 0
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}
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if (btbParams.nBHT > 0) {
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val bht = new BHT(btbParams.nBHT)
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if (btbParams.bhtParams.nonEmpty) {
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val bht = new BHT(btbParams.bhtParams.get)
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val isBranch = (idxHit & cfiType.map(_ === CFIType.branch).asUInt).orR
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val res = bht.get(io.req.bits.addr)
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when (io.req.valid && io.resp.valid && isBranch) {
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bht.advanceHistory(res.taken)
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}
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when (io.bht_advance.valid) {
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bht.advanceHistory(io.bht_advance.bits.bht.taken)
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}
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when (io.btb_update.valid) {
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bht.resetHistory(io.btb_update.bits.prediction.bits.bht)
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}
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when (io.bht_update.valid) {
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bht.updateTable(io.bht_update.bits.pc, io.bht_update.bits.prediction.bits.bht, io.bht_update.bits.taken)
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when (io.bht_update.bits.branch) {
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bht.updateTable(io.bht_update.bits.pc, io.bht_update.bits.prediction, io.bht_update.bits.taken)
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when (io.bht_update.bits.mispredict) {
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bht.updateHistory(io.bht_update.bits.pc, io.bht_update.bits.prediction.bits.bht, io.bht_update.bits.taken)
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bht.updateHistory(io.bht_update.bits.pc, io.bht_update.bits.prediction, io.bht_update.bits.taken)
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}
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}.elsewhen (io.bht_update.bits.mispredict) {
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bht.resetHistory(io.bht_update.bits.prediction)
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}
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}
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when (!res.taken && isBranch) { io.resp.bits.taken := false }
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@ -292,7 +317,7 @@ class BTB(implicit p: Parameters) extends BtbModule {
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when (io.ras_update.valid) {
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when (io.ras_update.bits.cfiType === CFIType.call) {
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ras.push(io.ras_update.bits.returnAddr)
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}.elsewhen (io.ras_update.bits.cfiType === CFIType.ret && io.ras_update.bits.prediction.valid) {
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}.elsewhen (io.ras_update.bits.cfiType === CFIType.ret) {
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ras.pop()
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}
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}
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@ -28,7 +28,7 @@ class FrontendExceptions extends Bundle {
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}
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class FrontendResp(implicit p: Parameters) extends CoreBundle()(p) {
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val btb = Valid(new BTBResp)
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val btb = new BTBResp
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val pc = UInt(width = vaddrBitsExtended) // ID stage PC
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val data = UInt(width = fetchWidth * coreInstBits)
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val mask = Bits(width = fetchWidth)
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@ -86,6 +86,7 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
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val s2_pc = RegInit(t = UInt(width = vaddrBitsExtended), alignPC(io.reset_vector))
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val s2_btb_resp_valid = if (usingBTB) Reg(Bool()) else false.B
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val s2_btb_resp_bits = Reg(new BTBResp)
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val s2_btb_taken = s2_btb_resp_valid && s2_btb_resp_bits.taken
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val s2_tlb_resp = Reg(tlb.io.resp)
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val s2_xcpt = s2_tlb_resp.ae.inst || s2_tlb_resp.pf.inst
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val s2_speculative = Reg(init=Bool(false))
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@ -143,13 +144,14 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
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fq.io.enq.bits.data := icache.io.resp.bits.data
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fq.io.enq.bits.mask := UInt((1 << fetchWidth)-1) << s2_pc.extract(log2Ceil(fetchWidth)+log2Ceil(coreInstBytes)-1, log2Ceil(coreInstBytes))
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fq.io.enq.bits.replay := icache.io.resp.bits.replay || icache.io.s2_kill && !icache.io.resp.valid && !s2_xcpt
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fq.io.enq.bits.btb.valid := s2_btb_resp_valid
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fq.io.enq.bits.btb.bits := s2_btb_resp_bits
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fq.io.enq.bits.btb := s2_btb_resp_bits
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fq.io.enq.bits.btb.taken := s2_btb_taken
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fq.io.enq.bits.xcpt := s2_tlb_resp
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when (icache.io.resp.valid && icache.io.resp.bits.ae) { fq.io.enq.bits.xcpt.ae.inst := true }
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if (usingBTB) {
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val btb = Module(new BTB)
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btb.io.flush := false
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btb.io.req.valid := false
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btb.io.req.bits.addr := s1_pc
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btb.io.btb_update := io.cpu.btb_update
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@ -166,26 +168,18 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
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predicted_taken := Bool(true)
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}
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if (!coreParams.jumpInFrontend) {
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// push RAS speculatively
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btb.io.ras_update.valid := btb.io.req.valid && btb.io.resp.valid && btb.io.resp.bits.cfiType.isOneOf(CFIType.call, CFIType.ret)
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val returnAddrLSBs = btb.io.resp.bits.bridx +& 1
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btb.io.ras_update.bits.returnAddr :=
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Mux(returnAddrLSBs(log2Ceil(fetchWidth)), ntpc, s1_base_pc | ((returnAddrLSBs << log2Ceil(coreInstBytes)) & (fetchBytes - 1)))
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btb.io.ras_update.bits.cfiType := btb.io.resp.bits.cfiType
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btb.io.ras_update.bits.prediction.valid := true
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} else {
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val s2_btb_hit = s2_btb_resp_valid && s2_btb_resp_bits.taken
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val s2_base_pc = ~(~s2_pc | (fetchBytes-1))
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val taken_idx = Wire(UInt())
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val after_idx = Wire(UInt())
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val useRAS = Wire(init=false.B)
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val updateBTB = Wire(init=false.B)
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def scanInsns(idx: Int, prevValid: Bool, prevBits: UInt, prevTaken: Bool): Bool = {
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val prevRVI = prevValid && prevBits(1,0) === 3
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def insnIsRVC(bits: UInt) = bits(1,0) =/= 3
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val prevRVI = prevValid && !insnIsRVC(prevBits)
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val valid = fq.io.enq.bits.mask(idx) && !prevRVI
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val bits = fq.io.enq.bits.data(coreInstBits*(idx+1)-1, coreInstBits*idx)
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val rvc = bits(1,0) =/= 3
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val rvc = insnIsRVC(bits)
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val rviBits = Cat(bits, prevBits)
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val rviBranch = rviBits(6,0) === Instructions.BEQ.value.asUInt()(6,0)
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val rviJump = rviBits(6,0) === Instructions.JAL.value.asUInt()(6,0)
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@ -205,36 +199,46 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
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prevRVI && (rviJump || rviJALR || rviBranch && s2_btb_resp_bits.bht.taken) ||
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valid && (rvcJump || rvcJALR || rvcJR || rvcBranch && s2_btb_resp_bits.bht.taken)
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val predictReturn = btb.io.ras_head.valid && (prevRVI && rviReturn || valid && rvcReturn)
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val predictBranch =
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prevRVI && (rviJump || rviBranch && s2_btb_resp_bits.bht.taken) ||
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valid && (rvcJump || rvcBranch && s2_btb_resp_bits.bht.taken)
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val predictJump = prevRVI && rviJump || valid && rvcJump
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val predictBranch = s2_btb_resp_bits.bht.taken && (prevRVI && rviBranch || valid && rvcBranch)
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when (s2_valid && s2_btb_resp_valid && s2_btb_resp_bits.bridx === idx && valid && !rvc) {
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// The BTB has predicted that the middle of an RVI instruction is
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// a branch! Flush the BTB and the pipeline.
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btb.io.flush := true
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fq.io.enq.bits.replay := true
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}
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when (!prevTaken) {
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taken_idx := idx
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after_idx := idx + 1
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btb.io.ras_update.valid := fq.io.enq.fire() && !wrong_path && (prevRVI && (rviCall || rviReturn) || valid && (rvcCall || rvcReturn))
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btb.io.ras_update.bits.prediction.valid := true
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btb.io.ras_update.bits.cfiType := Mux(Mux(prevRVI, rviReturn, rvcReturn), CFIType.ret, CFIType.call)
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btb.io.ras_update.bits.cfiType := Mux(Mux(prevRVI, rviReturn, rvcReturn), CFIType.ret,
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Mux(Mux(prevRVI, rviCall, rvcCall), CFIType.call,
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Mux(Mux(prevRVI, rviBranch, rvcBranch), CFIType.branch,
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CFIType.jump)))
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when (!s2_btb_hit) {
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when (fq.io.enq.fire() && taken && !predictBranch && !predictReturn) {
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when (!s2_btb_taken) {
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when (fq.io.enq.fire() && taken && !predictBranch && !predictJump && !predictReturn) {
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wrong_path := true
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}
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when (s2_valid && predictReturn) {
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useRAS := true
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}
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when (s2_valid && predictBranch) {
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when (s2_valid && (predictBranch || predictJump)) {
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val pc = s2_base_pc | (idx*coreInstBytes)
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val npc =
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if (idx == 0) pc.asSInt + Mux(prevRVI, rviImm -& 2.S, rvcImm)
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else Mux(prevRVI, pc - coreInstBytes, pc).asSInt + Mux(prevRVI, rviImm, rvcImm)
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predicted_npc := npc.asUInt
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}
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}
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when (prevRVI && rviBranch || valid && rvcBranch) {
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btb.io.bht_advance.valid := fq.io.enq.fire() && !wrong_path && !s2_btb_resp_valid
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btb.io.bht_advance.valid := fq.io.enq.fire() && !wrong_path
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btb.io.bht_advance.bits := s2_btb_resp_bits
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}
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when (!s2_btb_resp_valid && (predictBranch && s2_btb_resp_bits.bht.strongly_taken || predictJump || predictReturn)) {
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updateBTB := true
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}
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}
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@ -252,25 +256,35 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
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}
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}
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when (!io.cpu.btb_update.valid) {
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val fetch_bubble_likely = !fq.io.mask(1)
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btb.io.btb_update.valid := fq.io.enq.fire() && !wrong_path && fetch_bubble_likely && updateBTB
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btb.io.btb_update.bits.prediction.entry := UInt(tileParams.btb.get.nEntries)
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btb.io.btb_update.bits.isValid := true
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btb.io.btb_update.bits.cfiType := btb.io.ras_update.bits.cfiType
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btb.io.btb_update.bits.br_pc := s2_base_pc | (taken_idx << log2Ceil(coreInstBytes))
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btb.io.btb_update.bits.pc := s2_base_pc
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}
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btb.io.ras_update.bits.returnAddr := s2_base_pc + (after_idx << log2Ceil(coreInstBytes))
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val taken = scanInsns(0, s2_partial_insn_valid, s2_partial_insn, false.B)
|
||||
when (useRAS) {
|
||||
predicted_npc := btb.io.ras_head.bits
|
||||
}
|
||||
when (fq.io.enq.fire() && s2_btb_hit) {
|
||||
when (fq.io.enq.fire() && (s2_btb_taken || taken)) {
|
||||
s2_partial_insn_valid := false
|
||||
}
|
||||
when (!s2_btb_hit) {
|
||||
fq.io.enq.bits.btb.bits.bridx := taken_idx
|
||||
when (!s2_btb_taken) {
|
||||
when (taken) {
|
||||
fq.io.enq.bits.btb.valid := true
|
||||
fq.io.enq.bits.btb.bits.taken := true
|
||||
fq.io.enq.bits.btb.bits.entry := UInt(tileParams.btb.get.nEntries)
|
||||
fq.io.enq.bits.btb.bridx := taken_idx
|
||||
fq.io.enq.bits.btb.taken := true
|
||||
fq.io.enq.bits.btb.entry := UInt(tileParams.btb.get.nEntries)
|
||||
when (fq.io.enq.fire()) { s2_redirect := true }
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
assert(!s2_partial_insn_valid || fq.io.enq.bits.mask(0))
|
||||
when (s2_redirect) { s2_partial_insn_valid := false }
|
||||
when (io.cpu.req.valid) { wrong_path := false }
|
||||
}
|
||||
|
||||
@ -12,7 +12,6 @@ class Instruction(implicit val p: Parameters) extends ParameterizedBundle with H
|
||||
val xcpt0 = new FrontendExceptions // exceptions on first half of instruction
|
||||
val xcpt1 = new FrontendExceptions // exceptions on second half of instruction
|
||||
val replay = Bool()
|
||||
val btb_hit = Bool()
|
||||
val rvc = Bool()
|
||||
val inst = new ExpandedInstruction
|
||||
val raw = UInt(width = 32)
|
||||
@ -34,13 +33,12 @@ class IBuf(implicit p: Parameters) extends CoreModule {
|
||||
val n = fetchWidth - 1
|
||||
val nBufValid = if (n == 0) UInt(0) else Reg(init=UInt(0, log2Ceil(fetchWidth)))
|
||||
val buf = Reg(io.imem.bits)
|
||||
val ibufBTBHit = Reg(Bool())
|
||||
val ibufBTBResp = Reg(new BTBResp)
|
||||
val pcWordMask = UInt(coreInstBytes*fetchWidth-1, vaddrBitsExtended)
|
||||
|
||||
val pcWordBits = io.imem.bits.pc.extract(log2Ceil(fetchWidth*coreInstBytes)-1, log2Ceil(coreInstBytes))
|
||||
val nReady = Wire(init = UInt(0, log2Ceil(fetchWidth+1)))
|
||||
val nIC = Mux(io.imem.bits.btb.valid && io.imem.bits.btb.bits.taken, io.imem.bits.btb.bits.bridx +& 1, UInt(fetchWidth)) - pcWordBits
|
||||
val nIC = Mux(io.imem.bits.btb.taken, io.imem.bits.btb.bridx +& 1, UInt(fetchWidth)) - pcWordBits
|
||||
val nICReady = nReady - nBufValid
|
||||
val nValid = Mux(io.imem.valid, nIC, UInt(0)) + nBufValid
|
||||
io.imem.ready := io.inst(0).ready && nReady >= nBufValid && (nICReady >= nIC || n >= nIC - nICReady)
|
||||
@ -52,7 +50,6 @@ class IBuf(implicit p: Parameters) extends CoreModule {
|
||||
val shiftedBuf = shiftInsnRight(buf.data(n*coreInstBits-1, coreInstBits), (nReady-1)(log2Ceil(n-1)-1,0))
|
||||
buf.data := Cat(buf.data(n*coreInstBits-1, (n-1)*coreInstBits), shiftedBuf((n-1)*coreInstBits-1, 0))
|
||||
buf.pc := buf.pc & ~pcWordMask | (buf.pc + (nReady << log2Ceil(coreInstBytes))) & pcWordMask
|
||||
ibufBTBResp.bridx := ibufBTBResp.bridx - nReady
|
||||
}
|
||||
when (io.imem.valid && nReady >= nBufValid && nICReady < nIC && n >= nIC - nICReady) {
|
||||
val shamt = pcWordBits + nICReady
|
||||
@ -60,9 +57,7 @@ class IBuf(implicit p: Parameters) extends CoreModule {
|
||||
buf := io.imem.bits
|
||||
buf.data := shiftInsnRight(io.imem.bits.data, shamt)(n*coreInstBits-1,0)
|
||||
buf.pc := io.imem.bits.pc & ~pcWordMask | (io.imem.bits.pc + (nICReady << log2Ceil(coreInstBytes))) & pcWordMask
|
||||
ibufBTBHit := io.imem.bits.btb.valid
|
||||
ibufBTBResp := io.imem.bits.btb.bits
|
||||
ibufBTBResp.bridx := io.imem.bits.btb.bits.bridx + nICReady
|
||||
ibufBTBResp := io.imem.bits.btb
|
||||
}
|
||||
}
|
||||
when (io.kill) {
|
||||
@ -81,12 +76,9 @@ class IBuf(implicit p: Parameters) extends CoreModule {
|
||||
val xcpt = (0 until bufMask.getWidth).map(i => Mux(bufMask(i), buf.xcpt, io.imem.bits.xcpt))
|
||||
val buf_replay = Mux(buf.replay, bufMask, UInt(0))
|
||||
val ic_replay = buf_replay | Mux(io.imem.bits.replay, valid & ~bufMask, UInt(0))
|
||||
val ibufBTBHitMask = Mux(ibufBTBHit, UIntToOH(ibufBTBResp.bridx), UInt(0))
|
||||
assert(!io.imem.valid || !io.imem.bits.btb.valid || io.imem.bits.btb.bits.bridx >= pcWordBits)
|
||||
val icBTBHitMask = Mux(io.imem.bits.btb.valid, UIntToOH(io.imem.bits.btb.bits.bridx +& nBufValid - pcWordBits), UInt(0))
|
||||
val btbHitMask = ibufBTBHitMask & bufMask | icBTBHitMask & ~bufMask
|
||||
assert(!io.imem.valid || !io.imem.bits.btb.taken || io.imem.bits.btb.bridx >= pcWordBits)
|
||||
|
||||
io.btb_resp := Mux((ibufBTBHitMask & bufMask).orR, ibufBTBResp, io.imem.bits.btb.bits)
|
||||
io.btb_resp := io.imem.bits.btb
|
||||
io.pc := Mux(nBufValid > 0, buf.pc, io.imem.bits.pc)
|
||||
expand(0, 0, inst)
|
||||
|
||||
@ -97,15 +89,16 @@ class IBuf(implicit p: Parameters) extends CoreModule {
|
||||
io.inst(i).bits.raw := curInst
|
||||
|
||||
if (usingCompressed) {
|
||||
val replay = ic_replay(j) || (!exp.io.rvc && (btbHitMask(j) || ic_replay(j+1)))
|
||||
val replay = ic_replay(j) || (!exp.io.rvc && ic_replay(j+1))
|
||||
val full_insn = exp.io.rvc || valid(j+1) || buf_replay(j)
|
||||
io.inst(i).valid := valid(j) && full_insn
|
||||
io.inst(i).bits.xcpt0 := xcpt(j)
|
||||
io.inst(i).bits.xcpt1 := Mux(exp.io.rvc, 0.U, xcpt(j+1).asUInt).asTypeOf(new FrontendExceptions)
|
||||
io.inst(i).bits.replay := replay
|
||||
io.inst(i).bits.btb_hit := btbHitMask(j) || (!exp.io.rvc && btbHitMask(j+1))
|
||||
io.inst(i).bits.rvc := exp.io.rvc
|
||||
|
||||
when ((bufMask(j) && exp.io.rvc) || bufMask(j+1)) { io.btb_resp := ibufBTBResp }
|
||||
|
||||
when (full_insn && (i == 0 || io.inst(i).ready)) { nReady := Mux(exp.io.rvc, j+1, j+2) }
|
||||
|
||||
expand(i+1, Mux(exp.io.rvc, j+1, j+2), Mux(exp.io.rvc, curInst >> 16, curInst >> 32))
|
||||
@ -116,7 +109,6 @@ class IBuf(implicit p: Parameters) extends CoreModule {
|
||||
io.inst(i).bits.xcpt1 := 0.U.asTypeOf(new FrontendExceptions)
|
||||
io.inst(i).bits.replay := ic_replay(i)
|
||||
io.inst(i).bits.rvc := false
|
||||
io.inst(i).bits.btb_hit := btbHitMask(i)
|
||||
|
||||
expand(i+1, null, curInst >> 32)
|
||||
}
|
||||
|
||||
@ -30,7 +30,6 @@ case class RocketCoreParams(
|
||||
mtvecWritable: Boolean = true,
|
||||
fastLoadWord: Boolean = true,
|
||||
fastLoadByte: Boolean = false,
|
||||
jumpInFrontend: Boolean = true,
|
||||
tileControlAddr: Option[BigInt] = None,
|
||||
mulDiv: Option[MulDivParams] = Some(MulDivParams()),
|
||||
fpu: Option[FPUParams] = Some(FPUParams())
|
||||
@ -123,7 +122,6 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
|
||||
val ex_reg_xcpt_interrupt = Reg(Bool())
|
||||
val ex_reg_valid = Reg(Bool())
|
||||
val ex_reg_rvc = Reg(Bool())
|
||||
val ex_reg_btb_hit = Reg(Bool())
|
||||
val ex_reg_btb_resp = Reg(new BTBResp)
|
||||
val ex_reg_xcpt = Reg(Bool())
|
||||
val ex_reg_flush_pipe = Reg(Bool())
|
||||
@ -137,7 +135,6 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
|
||||
val mem_reg_xcpt_interrupt = Reg(Bool())
|
||||
val mem_reg_valid = Reg(Bool())
|
||||
val mem_reg_rvc = Reg(Bool())
|
||||
val mem_reg_btb_hit = Reg(Bool())
|
||||
val mem_reg_btb_resp = Reg(new BTBResp)
|
||||
val mem_reg_xcpt = Reg(Bool())
|
||||
val mem_reg_replay = Reg(Bool())
|
||||
@ -292,7 +289,6 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
|
||||
ex_reg_replay := !take_pc && ibuf.io.inst(0).valid && ibuf.io.inst(0).bits.replay
|
||||
ex_reg_xcpt := !ctrl_killd && id_xcpt
|
||||
ex_reg_xcpt_interrupt := !take_pc && ibuf.io.inst(0).valid && csr.io.interrupt
|
||||
ex_reg_btb_hit := ibuf.io.inst(0).bits.btb_hit
|
||||
|
||||
when (!ctrl_killd) {
|
||||
ex_ctrl := id_ctrl
|
||||
@ -374,7 +370,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
|
||||
val mem_int_wdata = Mux(!mem_reg_xcpt && (mem_ctrl.jalr ^ mem_npc_misaligned), mem_br_target, mem_reg_wdata.asSInt).asUInt
|
||||
val mem_cfi = mem_ctrl.branch || mem_ctrl.jalr || mem_ctrl.jal
|
||||
val mem_cfi_taken = (mem_ctrl.branch && mem_br_taken) || mem_ctrl.jalr || mem_ctrl.jal
|
||||
val mem_direction_misprediction = (Bool(coreParams.jumpInFrontend) || mem_reg_btb_hit) && mem_ctrl.branch && mem_br_taken =/= mem_reg_btb_resp.taken
|
||||
val mem_direction_misprediction = mem_ctrl.branch && mem_br_taken =/= (usingBTB && mem_reg_btb_resp.taken)
|
||||
val mem_misprediction = if (usingBTB) mem_wrong_npc else mem_cfi_taken
|
||||
take_pc_mem := mem_reg_valid && (mem_misprediction || mem_reg_sfence)
|
||||
|
||||
@ -393,7 +389,6 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
|
||||
mem_reg_load := ex_ctrl.mem && isRead(ex_ctrl.mem_cmd)
|
||||
mem_reg_store := ex_ctrl.mem && isWrite(ex_ctrl.mem_cmd)
|
||||
mem_reg_sfence := ex_sfence
|
||||
mem_reg_btb_hit := ex_reg_btb_hit
|
||||
mem_reg_btb_resp := ex_reg_btb_resp
|
||||
mem_reg_flush_pipe := ex_reg_flush_pipe
|
||||
mem_reg_slow_bypass := ex_slow_bypass
|
||||
@ -608,8 +603,8 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
|
||||
|
||||
ibuf.io.inst(0).ready := !ctrl_stalld
|
||||
|
||||
io.imem.btb_update.valid := (mem_reg_replay && mem_reg_btb_hit) || (mem_reg_valid && !take_pc_wb && mem_wrong_npc && (!mem_cfi || mem_cfi_taken))
|
||||
io.imem.btb_update.bits.isValid := !mem_reg_replay && mem_cfi
|
||||
io.imem.btb_update.valid := mem_reg_valid && !take_pc_wb && mem_wrong_npc && (!mem_cfi || mem_cfi_taken)
|
||||
io.imem.btb_update.bits.isValid := mem_cfi
|
||||
io.imem.btb_update.bits.cfiType :=
|
||||
Mux((mem_ctrl.jal || mem_ctrl.jalr) && mem_waddr(0), CFIType.call,
|
||||
Mux(mem_ctrl.jalr && mem_reg_inst(19,15) === BitPat("b00?01"), CFIType.ret,
|
||||
@ -618,14 +613,14 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
|
||||
io.imem.btb_update.bits.target := io.imem.req.bits.pc
|
||||
io.imem.btb_update.bits.br_pc := (if (usingCompressed) mem_reg_pc + Mux(mem_reg_rvc, UInt(0), UInt(2)) else mem_reg_pc)
|
||||
io.imem.btb_update.bits.pc := ~(~io.imem.btb_update.bits.br_pc | (coreInstBytes*fetchWidth-1))
|
||||
io.imem.btb_update.bits.prediction.valid := mem_reg_btb_hit
|
||||
io.imem.btb_update.bits.prediction.bits := mem_reg_btb_resp
|
||||
io.imem.btb_update.bits.prediction := mem_reg_btb_resp
|
||||
|
||||
io.imem.bht_update.valid := mem_reg_valid && !take_pc_wb && mem_ctrl.branch
|
||||
io.imem.bht_update.valid := mem_reg_valid && !take_pc_wb
|
||||
io.imem.bht_update.bits.pc := io.imem.btb_update.bits.pc
|
||||
io.imem.bht_update.bits.taken := mem_br_taken
|
||||
io.imem.bht_update.bits.mispredict := mem_wrong_npc
|
||||
io.imem.bht_update.bits.prediction := io.imem.btb_update.bits.prediction
|
||||
io.imem.bht_update.bits.branch := mem_ctrl.branch
|
||||
io.imem.bht_update.bits.prediction := mem_reg_btb_resp.bht
|
||||
|
||||
io.fpu.valid := !ctrl_killd && id_ctrl.fp
|
||||
io.fpu.killx := ctrl_killx
|
||||
|
||||
@ -33,7 +33,6 @@ trait CoreParams {
|
||||
val nL2TLBEntries: Int
|
||||
val mtvecInit: Option[BigInt]
|
||||
val mtvecWritable: Boolean
|
||||
val jumpInFrontend: Boolean
|
||||
val tileControlAddr: Option[BigInt]
|
||||
|
||||
def instBytes: Int = instBits / 8
|
||||
|
||||
@ -38,45 +38,47 @@ class SeqRandom(n_ways: Int) extends SeqReplacementPolicy {
|
||||
|
||||
class PseudoLRU(n: Int)
|
||||
{
|
||||
require(isPow2(n))
|
||||
val state_reg = Reg(Bits(width = n))
|
||||
private val state_reg = Reg(UInt(width = n-1))
|
||||
def access(way: UInt) {
|
||||
state_reg := get_next_state(state_reg,way)
|
||||
}
|
||||
def get_next_state(state: UInt, way: UInt) = {
|
||||
var next_state = state
|
||||
var next_state = state << 1
|
||||
var idx = UInt(1,1)
|
||||
for (i <- log2Up(n)-1 to 0 by -1) {
|
||||
val bit = way(i)
|
||||
next_state = next_state.bitSet(idx, !bit)
|
||||
idx = Cat(idx, bit)
|
||||
}
|
||||
next_state
|
||||
next_state(n-1, 1)
|
||||
}
|
||||
def replace = get_replace_way(state_reg)
|
||||
def get_replace_way(state: Bits) = {
|
||||
def get_replace_way(state: UInt) = {
|
||||
val shifted_state = state << 1
|
||||
var idx = UInt(1,1)
|
||||
for (i <- 0 until log2Up(n))
|
||||
idx = Cat(idx, state(idx))
|
||||
for (i <- log2Up(n)-1 to 0 by -1) {
|
||||
val in_bounds = Cat(idx, UInt(BigInt(1) << i))(log2Up(n)-1, 0) < UInt(n)
|
||||
idx = Cat(idx, in_bounds && shifted_state(idx))
|
||||
}
|
||||
idx(log2Up(n)-1,0)
|
||||
}
|
||||
}
|
||||
|
||||
class SeqPLRU(n_sets: Int, n_ways: Int) extends SeqReplacementPolicy {
|
||||
val state = SeqMem(n_sets, Bits(width = n_ways-1))
|
||||
val state = SeqMem(n_sets, UInt(width = n_ways-1))
|
||||
val logic = new PseudoLRU(n_ways)
|
||||
val current_state = Wire(Bits())
|
||||
val current_state = Wire(UInt())
|
||||
val plru_way = logic.get_replace_way(current_state)
|
||||
val next_state = Wire(Bits())
|
||||
val next_state = Wire(UInt())
|
||||
|
||||
def access(set: UInt) = {
|
||||
current_state := Cat(state.read(set), Bits(0, width = 1))
|
||||
current_state := state.read(set)
|
||||
}
|
||||
|
||||
def update(valid: Bool, hit: Bool, set: UInt, way: UInt) = {
|
||||
val update_way = Mux(hit, way, plru_way)
|
||||
next_state := logic.get_next_state(current_state, update_way)
|
||||
when (valid) { state.write(set, next_state(n_ways-1,1)) }
|
||||
when (valid) { state.write(set, next_state) }
|
||||
}
|
||||
|
||||
def way = plru_way
|
||||
|
||||
Loading…
Reference in New Issue
Block a user