riscv/rocket-chip
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Merge pull request #1098 from freechipsproject/frontend

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Frontend improvements
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Andrew Waterman authored and GitHub committed 2017-11-09 17:44:38 -08:00
2 parents 50ce3f5086 d0c6cbba6b
commit efdb418559
6 files changed
+198 -171
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src/main/scala/tile/Core.scala
-1
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@@ -33,7 +33,6 @@ trait CoreParams {
val nL2TLBEntries: Int
val mtvecInit: Option[BigInt]
val mtvecWritable: Boolean
val jumpInFrontend: Boolean
val tileControlAddr: Option[BigInt]
def instBytes: Int = instBits / 8