riscv/rocket-chip
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Miscellaneous periphery improvements (#689)

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* fifofixer: work around zero-width wires for single source id
* periphery: sourceshrinker takes maxInFlight parameter
This commit is contained in:
Henry Cook 2017-04-20 11:28:00 -07:00 committed by Wesley W. Terpstra
parent 9002e7e532
commit ef8a819763
2 changed files with 3 additions and 3 deletions
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2
src/main/scala/rocketchip/Periphery.scala
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@ -253,7 +253,7 @@ trait PeripheryMasterTLMMIO {
mmio_tl := mmio_tl :=
TLBuffer()( TLBuffer()(
TLSourceShrinker(config.idBits)( TLSourceShrinker(1 << config.idBits)(
TLWidthWidget(socBusConfig.beatBytes)( TLWidthWidget(socBusConfig.beatBytes)(
socBus.node))) socBus.node)))
} }

4
src/main/scala/uncore/tilelink2/FIFOFixer.scala
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@ -32,8 +32,8 @@ class TLFIFOFixer(implicit p: Parameters) extends LazyModule
val stalls = edgeIn.client.clients.filter(c => c.requestFifo && c.sourceId.size > 1).map { c => val stalls = edgeIn.client.clients.filter(c => c.requestFifo && c.sourceId.size > 1).map { c =>
val a_sel = c.sourceId.contains(in.a.bits.source) val a_sel = c.sourceId.contains(in.a.bits.source)
val d_sel = c.sourceId.contains(in.d.bits.source) val d_sel = c.sourceId.contains(in.d.bits.source)
val id = RegInit(UInt(0, width = log2Ceil(maxId+1))) val id = RegInit(UInt(0, width = log2Up(maxId+1))) // TODO zero-width
val count = RegInit(UInt(0, width = log2Ceil(c.sourceId.size+1))) val count = RegInit(UInt(0, width = log2Up(c.sourceId.size+1))) // TODO zero-width
val a_inc = in.a.fire() && a_first && a_sel val a_inc = in.a.fire() && a_first && a_sel
val d_dec = in.d.fire() && d_first && d_sel val d_dec = in.d.fire() && d_first && d_sel