riscv/rocket-chip
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RocketChip: handle atomics only if needed

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Wesley W. Terpstra 2016-06-01 16:09:25 -07:00 committed by Andrew Waterman
parent 3e0ec855cf
commit ef27cc3a33
1 changed files with 3 additions and 3 deletions
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6
src/main/scala/RocketChip.scala
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@ -143,7 +143,7 @@ class Top(topParams: Parameters) extends Module with HasTopLevelParameters {
val io = new TopIO val io = new TopIO
// Build an Uncore and a set of Tiles // Build an Uncore and a set of Tiles
val innerTLParams = p.alterPartial({case TLId => "L1toL2" }) val innerTLParams = p.alterPartial({case HastiId => "TL" case TLId => "L1toL2" })
val uncore = Module(new Uncore()(innerTLParams)) val uncore = Module(new Uncore()(innerTLParams))
val tileList = uncore.io.prci zip p(BuildTiles) map { case(prci, tile) => tile(prci.reset, p) } val tileList = uncore.io.prci zip p(BuildTiles) map { case(prci, tile) => tile(prci.reset, p) }
@ -255,7 +255,7 @@ class Uncore(implicit val p: Parameters) extends Module
require (mmio_axi + mmio_ahb <= 1) require (mmio_axi + mmio_ahb <= 1)
if (mmio_ahb == 1) { if (mmio_ahb == 1) {
val ahb = Module(new AHBBridge) val ahb = Module(new AHBBridge(true)) // with atomics
io.mmio_ahb(0) <> ahb.io.ahb io.mmio_ahb(0) <> ahb.io.ahb
ahb.io.tl <> ext ahb.io.tl <> ext
} else { } else {
@ -343,7 +343,7 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
// Abuse the fact that zip takes the shorter of the two lists // Abuse the fact that zip takes the shorter of the two lists
for ((ahb, tl) <- io.mem_ahb zip mem_ic.io.out) { for ((ahb, tl) <- io.mem_ahb zip mem_ic.io.out) {
val bridge = Module(new AHBBridge) val bridge = Module(new AHBBridge(false)) // no atomics
ahb <> bridge.io.ahb ahb <> bridge.io.ahb
bridge.io.tl <> tl bridge.io.tl <> tl
} }