riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

debug: Enforce mapping between hartsel and hartid, use more reasonable defaults for DATA and PROGBUF sizes.

Browse Source
This commit is contained in:
Megan Wachs 2017-04-04 11:07:33 -07:00 committed by Andrew Waterman
parent 127f121ef2
commit eef05cc1fc
1 changed files with 19 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

30
src/main/scala/uncore/devices/debug/Debug.scala
View File

@ -122,7 +122,9 @@ case class DebugModuleConfig (
hasAccess8 : Boolean, hasAccess8 : Boolean,
nSerialPorts : Int, nSerialPorts : Int,
supportQuickAccess : Boolean, supportQuickAccess : Boolean,
supportHartArray : Boolean supportHartArray : Boolean,
hartidToHartSel : (UInt) => UInt,
hartSelToHartId : (UInt) => UInt
) { ) {
if (hasBusMaster == false){ if (hasBusMaster == false){
@ -149,10 +151,9 @@ case class DebugModuleConfig (
class DefaultDebugModuleConfig (val xlen:Int /*TODO , val configStringAddr: Int*/) class DefaultDebugModuleConfig (val xlen:Int /*TODO , val configStringAddr: Int*/)
extends DebugModuleConfig( extends DebugModuleConfig(
nDMIAddrSize = 7, nDMIAddrSize = 7,
//TODO use more words to support arbitrary sequences. nProgramBufferWords = 16,
nProgramBufferWords = 15,
// TODO use less for small XLEN? // TODO use less for small XLEN?
nAbstractDataWords = 4, nAbstractDataWords = (if (xlen == 32) 1 else if (xlen == 64) 2 else 4),
nScratch = 1, nScratch = 1,
hasBusMaster = false, hasBusMaster = false,
hasAccess128 = false, hasAccess128 = false,
@ -162,9 +163,10 @@ class DefaultDebugModuleConfig (val xlen:Int /*TODO , val configStringAddr: Int*
hasAccess8 = false, hasAccess8 = false,
nSerialPorts = 0, nSerialPorts = 0,
supportQuickAccess = false, supportQuickAccess = false,
supportHartArray = false supportHartArray = false,
// TODO configStringAddr = configStringAddr // TODO configStringAddr = configStringAddr
// TODO: accept a mapping function from HARTID -> HARTSEL hartIdToHartSel = (x: UInt) => x,
hartSelToHartId = (x: UInt) => x
) )
case object DMKey extends Field[DebugModuleConfig] case object DMKey extends Field[DebugModuleConfig]
@ -696,11 +698,11 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
haltedBitRegs(component) := false.B haltedBitRegs(component) := false.B
}.otherwise { }.otherwise {
when (hartHaltedWrEn) { when (hartHaltedWrEn) {
when (hartHaltedId === component.U) { when (hartIdToHartSel(hartHaltedId) === component.U) {
haltedBitRegs(component) := true.B haltedBitRegs(component) := true.B
} }
}.elsewhen (hartResumingWrEn) { }.elsewhen (hartResumingWrEn) {
when (hartResumingId === component.U) { when (hartIdToHartSel(hartResumingId) === component.U) {
haltedBitRegs(component) := false.B haltedBitRegs(component) := false.B
} }
} }
@ -774,8 +776,10 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
} }
} }
val goBytes = Wire(init = Vec.fill(nComponents){0.U(8.W)}) val goBytes = Wire(init = Vec.fill(1024){0.U(8.W)})
goBytes(selectedHartReg) := Cat(0.U(7.W), goReg) goBytes(hartSelToHartId(selectedHartReg)) := Cat(0.U(7.W), goReg)
assert ((hartSelToHartId(selectedHartReg) < 1024),
"HartSel to HartId Mapping is illegal for this Debug Implementation, because HartID must be < 1024 for it to work");
//---------------------------- //----------------------------
// Abstract Command Decoding & Generation // Abstract Command Decoding & Generation
@ -976,7 +980,7 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
// We can't just look at 'hartHalted' here, because // We can't just look at 'hartHalted' here, because
// hartHaltedWrEn is overloaded to mean 'got an ebreak' // hartHaltedWrEn is overloaded to mean 'got an ebreak'
// which may have happened when we were already halted. // which may have happened when we were already halted.
when(goReg === false.B && hartHaltedWrEn && (hartHaltedId === selectedHartReg)){ when(goReg === false.B && hartHaltedWrEn && (hartIdToHartSel(hartHaltedId) === selectedHartReg)){
ctrlStateNxt := CtrlState(Abstract) ctrlStateNxt := CtrlState(Abstract)
goAbstract := true.B goAbstract := true.B
} }
@ -990,7 +994,7 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
// We can't just look at 'hartHalted' here, because // We can't just look at 'hartHalted' here, because
// hartHaltedWrEn is overloaded to mean 'got an ebreak' // hartHaltedWrEn is overloaded to mean 'got an ebreak'
// which may have happened when we were already halted. // which may have happened when we were already halted.
when(goReg === false.B && hartHaltedWrEn && (hartHaltedId === selectedHartReg)){ when(goReg === false.B && hartHaltedWrEn && (hartIdToHartSel(hartHaltedId) === selectedHartReg)){
when (accessRegisterCommandReg.postexec) { when (accessRegisterCommandReg.postexec) {
ctrlStateNxt := CtrlState(PostExec) ctrlStateNxt := CtrlState(PostExec)
goProgramBuffer := true.B goProgramBuffer := true.B
@ -1008,7 +1012,7 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
// We can't just look at 'hartHalted' here, because // We can't just look at 'hartHalted' here, because
// hartHaltedWrEn is overloaded to mean 'got an ebreak' // hartHaltedWrEn is overloaded to mean 'got an ebreak'
// which may have happened when we were already halted. // which may have happened when we were already halted.
when(goReg === false.B && hartHaltedWrEn && (hartHaltedId === selectedHartReg)){ when(goReg === false.B && hartHaltedWrEn && (hartIdToHartSel(hartHaltedId) === selectedHartReg)){
ctrlStateNxt := CtrlState(Waiting) ctrlStateNxt := CtrlState(Waiting)
} }
when(hartExceptionWrEn) { when(hartExceptionWrEn) {