riscv/rocket-chip
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separate memory request command and data

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also, merge some VLSI/C++ test harness functionality
This commit is contained in:
Andrew Waterman 2012-02-28 18:59:15 -08:00
parent e15284d22c
commit eec369a1c7
1 changed files with 0 additions and 6 deletions
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6
uncore/coherence.scala
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@ -424,12 +424,6 @@ class CoherenceHubNoDir extends CoherenceHub {
//mem_req_arb.io.out.ready := io.mem.req_cmd.ready || io.mem.req_data.ready //mem_req_arb.io.out.ready := io.mem.req_cmd.ready || io.mem.req_data.ready
io.mem.req_cmd <> mem_req_arb.io.out.bits.req_cmd io.mem.req_cmd <> mem_req_arb.io.out.bits.req_cmd
io.mem.req_data <> mem_req_arb.io.out.bits.req_data io.mem.req_data <> mem_req_arb.io.out.bits.req_data
//io.mem.req_wdata := MuxLookup(mem_req_arb.io.out.bits.data_idx,
// Bits(0, width = MEM_DATA_BITS),
// (0 until NTILES).map( j =>
// UFix(j) -> Mux(mem_req_arb.io.out.bits.is_probe_rep,
// io.tiles(j).probe_rep_data.bits.data,
// io.tiles(j).xact_init_data.bits.data)))
// Handle probe replies, which may or may not have data // Handle probe replies, which may or may not have data
for( j <- 0 until NTILES ) { for( j <- 0 until NTILES ) {