add fcvt.s.d, fcvt.d.s
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ce202c73d1
commit
ee9fc10668
@ -101,6 +101,8 @@ class rocketFPUDecoder extends Component
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FCVT_WU_D-> List(Y,FCMD_CVT_WU_FMT,N,N,Y,N,N,N,N,Y,N,N,N,N,N),
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FCVT_L_D -> List(Y,FCMD_CVT_L_FMT, N,N,Y,N,N,N,N,Y,N,N,N,N,N),
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FCVT_LU_D-> List(Y,FCMD_CVT_LU_FMT,N,N,Y,N,N,N,N,Y,N,N,N,N,N),
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FCVT_S_D -> List(Y,FCMD_CVT_FMT_D, Y,N,Y,N,N,Y,N,N,Y,N,N,N,N),
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FCVT_D_S -> List(Y,FCMD_CVT_FMT_S, Y,N,Y,N,N,N,N,N,Y,N,N,N,N),
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FEQ_S -> List(Y,FCMD_EQ, N,N,Y,Y,N,Y,N,Y,N,N,N,N,N),
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FLT_S -> List(Y,FCMD_LT, N,N,Y,Y,N,Y,N,Y,N,N,N,N,N),
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FLE_S -> List(Y,FCMD_LE, N,N,Y,Y,N,Y,N,Y,N,N,N,N,N),
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@ -167,6 +169,7 @@ class rocketFPIntUnit extends Component
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val io = new Bundle {
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val single = Bool(INPUT)
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val cmd = Bits(FCMD_WIDTH, INPUT)
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val rm = Bits(3, INPUT)
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val fsr = Bits(FSR_WIDTH, INPUT)
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val in1 = Bits(65, INPUT)
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val in2 = Bits(65, INPUT)
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@ -190,7 +193,7 @@ class rocketFPIntUnit extends Component
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val s2i = new hardfloat.recodedFloat32ToAny
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s2i.io.in := io.in1
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s2i.io.roundingMode := io.fsr >> UFix(5)
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s2i.io.roundingMode := io.rm
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s2i.io.typeOp := ~io.cmd(1,0)
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val dcmp = new hardfloat.recodedFloat64Compare
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@ -201,7 +204,7 @@ class rocketFPIntUnit extends Component
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val d2i = new hardfloat.recodedFloat64ToAny
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d2i.io.in := io.in1
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d2i.io.roundingMode := io.fsr >> UFix(5)
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d2i.io.roundingMode := io.rm
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d2i.io.typeOp := ~io.cmd(1,0)
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// output muxing
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@ -243,7 +246,7 @@ class rocketFPUFastPipe extends Component
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val io = new Bundle {
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val single = Bool(INPUT)
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val cmd = Bits(FCMD_WIDTH, INPUT)
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val fsr = Bits(FSR_WIDTH, INPUT)
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val rm = Bits(3, INPUT)
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val fromint = Bits(64, INPUT)
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val in1 = Bits(65, INPUT)
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val in2 = Bits(65, INPUT)
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@ -261,12 +264,12 @@ class rocketFPUFastPipe extends Component
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val i2s = new hardfloat.anyToRecodedFloat32
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i2s.io.in := io.fromint
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i2s.io.roundingMode := io.fsr >> UFix(5)
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i2s.io.roundingMode := io.rm
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i2s.io.typeOp := ~io.cmd(1,0)
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val i2d = new hardfloat.anyToRecodedFloat64
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i2d.io.in := io.fromint
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i2d.io.roundingMode := io.fsr >> UFix(5)
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i2d.io.roundingMode := io.rm
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i2d.io.typeOp := ~io.cmd(1,0)
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// fp->fp units
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@ -279,6 +282,13 @@ class rocketFPUFastPipe extends Component
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val fsgnj = Cat(Mux(io.single, io.in1(64), sign_d), io.in1(63,33),
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Mux(io.single, sign_s, io.in1(32)), io.in1(31,0))
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val s2d = new hardfloat.recodedFloat32ToRecodedFloat64
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s2d.io.in := io.in1
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val d2s = new hardfloat.recodedFloat64ToRecodedFloat32
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d2s.io.in := io.in1
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d2s.io.roundingMode := io.rm
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// output muxing
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val (out_s, exc_s) = (Wire() { Bits() }, Wire() { Bits() })
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out_s := Reg(rec_s.io.out)
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@ -297,6 +307,12 @@ class rocketFPUFastPipe extends Component
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out_s := r_fsgnj(32,0)
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out_d := r_fsgnj
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}
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when (r_cmd === FCMD_CVT_FMT_S || r_cmd === FCMD_CVT_FMT_D) {
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out_s := Reg(d2s.io.out)
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exc_s := Reg(d2s.io.exceptionFlags)
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out_d := Reg(s2d.io.out)
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exc_d := Reg(s2d.io.exceptionFlags)
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}
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when (r_cmd === FCMD_CVT_FMT_W || r_cmd === FCMD_CVT_FMT_WU ||
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r_cmd === FCMD_CVT_FMT_L || r_cmd === FCMD_CVT_FMT_LU) {
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out_s := Reg(i2s.io.out)
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@ -360,6 +376,7 @@ class rocketFPU(sfma_latency: Int, dfma_latency: Int) extends Component
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val ex_rs1 = regfile.read(reg_inst(26,22))
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val ex_rs2 = regfile.read(reg_inst(21,17))
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val ex_rs3 = regfile.read(reg_inst(16,12))
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val ex_rm = Mux(reg_inst(11,9) === Bits(7), fsr_rm, reg_inst(11,9))
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val mem_fromint_val = Reg(resetVal = Bool(false))
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val mem_fromint_data = Reg() { Bits() }
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@ -367,12 +384,14 @@ class rocketFPU(sfma_latency: Int, dfma_latency: Int) extends Component
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val mem_rs1 = Reg() { Bits() }
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val mem_rs2 = Reg() { Bits() }
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val mem_rs3 = Reg() { Bits() }
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val mem_rm = Reg() { Bits() }
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val mem_wrfsr_val = Reg(resetVal = Bool(false))
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mem_fromint_val := Bool(false)
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mem_toint_val := Bool(false)
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mem_wrfsr_val := Bool(false)
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when (reg_valid) {
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mem_rm := ex_rm
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when (ctrl.fromint || ctrl.wrfsr) {
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mem_fromint_val := !io.ctrl.killx
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mem_fromint_data := io.dpath.fromint_data
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@ -383,30 +402,25 @@ class rocketFPU(sfma_latency: Int, dfma_latency: Int) extends Component
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when (ctrl.toint) {
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mem_toint_val := !io.ctrl.killx
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}
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when (ctrl.toint || ctrl.fastpipe) {
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mem_rs1 := ex_rs1
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when (ctrl.ren2) {
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mem_rs2 := ex_rs2
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}
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}
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when (ctrl.ren1) {
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mem_rs1 := ex_rs1
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}
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when (ctrl.store) {
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mem_rs1 := ex_rs2
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}
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when (ctrl.ren2) {
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mem_rs2 := ex_rs2
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}
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when (ctrl.ren3) {
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mem_rs3 := ex_rs3
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}
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when (ctrl.store) {
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mem_rs1 := ex_rs2
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}
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}
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// currently we assume FP stores and FP->int ops take 1 cycle (MEM)
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val fpiu = new rocketFPIntUnit
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fpiu.io.single := mem_ctrl.single
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fpiu.io.cmd := mem_ctrl.cmd
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fpiu.io.rm := mem_rm
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fpiu.io.fsr := Cat(fsr_rm, fsr_exc)
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fpiu.io.in1 := mem_rs1
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fpiu.io.in2 := mem_rs2
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@ -417,7 +431,7 @@ class rocketFPU(sfma_latency: Int, dfma_latency: Int) extends Component
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val fastpipe = new rocketFPUFastPipe
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fastpipe.io.single := mem_ctrl.single
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fastpipe.io.cmd := mem_ctrl.cmd
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fastpipe.io.fsr := Cat(fsr_rm, fsr_exc)
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fastpipe.io.rm := mem_rm
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fastpipe.io.fromint := mem_fromint_data
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fastpipe.io.in1 := mem_rs1
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fastpipe.io.in2 := mem_rs2
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@ -489,5 +503,5 @@ class rocketFPU(sfma_latency: Int, dfma_latency: Int) extends Component
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io.ctrl.nack := fsr_busy || units_busy || write_port_busy
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io.ctrl.dec <> fp_decoder.io.sigs
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// we don't currently support round-max-magnitude (rm=4)
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io.ctrl.illegal_rm := Mux(reg_inst(11,9) === Bits(7), fsr_rm(2), reg_inst(11))
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io.ctrl.illegal_rm := ex_rm(2)
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}
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