riscv/rocket-chip
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Support indexing 1-entry Seqs

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It's a zero-width wire special case.

Closes #706.
This commit is contained in:
Andrew Waterman 2017-04-26 12:19:21 -07:00
parent 2e23d46631
commit ee6702e5e0
1 changed files with 3 additions and 1 deletions
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4
src/main/scala/util/Package.scala
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@ -11,7 +11,9 @@ package object util {
implicit class SeqToAugmentedSeq[T <: Data](val x: Seq[T]) extends AnyVal { implicit class SeqToAugmentedSeq[T <: Data](val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = { def apply(idx: UInt): T = {
if (!isPow2(x.size)) { if (x.size == 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder // For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx) (x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else { } else {