riscv/rocket-chip
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get rid of Vec.fill in IOs

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This commit is contained in:
Howard Mao 2015-09-22 10:30:09 -07:00
parent 64ab45e2e4
commit ee65f6a84d
2 changed files with 8 additions and 8 deletions
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14
junctions/src/main/scala/nasti.scala
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@ -238,7 +238,7 @@ class MemIONASTISlaveIOConverter(cacheBlockOffsetBits: Int) extends MIFModule wi
/** Arbitrate among arbN masters requesting to a single slave */ /** Arbitrate among arbN masters requesting to a single slave */
class NASTIArbiter(val arbN: Int) extends NASTIModule { class NASTIArbiter(val arbN: Int) extends NASTIModule {
val io = new Bundle { val io = new Bundle {
val master = Vec.fill(arbN) { new NASTISlaveIO } val master = Vec(new NASTISlaveIO, arbN)
val slave = new NASTIMasterIO val slave = new NASTIMasterIO
} }
@ -306,7 +306,7 @@ class NASTIArbiter(val arbN: Int) extends NASTIModule {
* Arbiter locks until last message in channel is sent */ * Arbiter locks until last message in channel is sent */
class NASTIReadDataArbiter(arbN: Int) extends NASTIModule { class NASTIReadDataArbiter(arbN: Int) extends NASTIModule {
val io = new Bundle { val io = new Bundle {
val in = Vec.fill(arbN) { Decoupled(new NASTIReadDataChannel) }.flip val in = Vec(Decoupled(new NASTIReadDataChannel), arbN).flip
val out = Decoupled(new NASTIReadDataChannel) val out = Decoupled(new NASTIReadDataChannel)
} }
@ -402,7 +402,7 @@ class NASTIRouter(addrmap: Seq[(BigInt, BigInt)]) extends NASTIModule {
val io = new Bundle { val io = new Bundle {
val master = new NASTISlaveIO val master = new NASTISlaveIO
val slave = Vec.fill(nSlaves) { new NASTIMasterIO } val slave = Vec(new NASTIMasterIO, nSlaves)
} }
var ar_ready = Bool(false) var ar_ready = Bool(false)
@ -479,8 +479,8 @@ class NASTIRouter(addrmap: Seq[(BigInt, BigInt)]) extends NASTIModule {
class NASTICrossbar(nMasters: Int, nSlaves: Int, addrmap: Seq[(BigInt, BigInt)]) class NASTICrossbar(nMasters: Int, nSlaves: Int, addrmap: Seq[(BigInt, BigInt)])
extends NASTIModule { extends NASTIModule {
val io = new Bundle { val io = new Bundle {
val masters = Vec.fill(nMasters) { new NASTISlaveIO } val masters = Vec(new NASTISlaveIO, nMasters)
val slaves = Vec.fill(nSlaves) { new NASTIMasterIO } val slaves = Vec(new NASTIMasterIO, nSlaves)
} }
val routers = Vec.fill(nMasters) { Module(new NASTIRouter(addrmap)).io } val routers = Vec.fill(nMasters) { Module(new NASTIRouter(addrmap)).io }
@ -594,8 +594,8 @@ case object NASTIAddrHashMap extends Field[AddrHashMap]
class NASTIInterconnectIO(val nMasters: Int, val nSlaves: Int) extends Bundle { class NASTIInterconnectIO(val nMasters: Int, val nSlaves: Int) extends Bundle {
/* This is a bit confusing. The interconnect is a slave to the masters and /* This is a bit confusing. The interconnect is a slave to the masters and
* a master to the slaves. Hence why the declarations seem to be backwards. */ * a master to the slaves. Hence why the declarations seem to be backwards. */
val masters = Vec.fill(nMasters) { new NASTISlaveIO } val masters = Vec(new NASTISlaveIO, nMasters)
val slaves = Vec.fill(nSlaves) { new NASTIMasterIO } val slaves = Vec(new NASTIMasterIO, nSlaves)
override def cloneType = override def cloneType =
new NASTIInterconnectIO(nMasters, nSlaves).asInstanceOf[this.type] new NASTIInterconnectIO(nMasters, nSlaves).asInstanceOf[this.type]
} }

2
junctions/src/main/scala/smi.scala
View File

@ -58,7 +58,7 @@ class SMIMem(val dataWidth: Int, val memDepth: Int) extends SMIPeripheral {
class SMIArbiter(val n: Int, val dataWidth: Int, val addrWidth: Int) class SMIArbiter(val n: Int, val dataWidth: Int, val addrWidth: Int)
extends Module { extends Module {
val io = new Bundle { val io = new Bundle {
val in = Vec.fill(n) { new SMIIO(dataWidth, addrWidth) }.flip val in = Vec(new SMIIO(dataWidth, addrWidth), n).flip
val out = new SMIIO(dataWidth, addrWidth) val out = new SMIIO(dataWidth, addrWidth)
} }