tilelink: rewrite WidthWidget beat splitter
- split the data based on the address, not the mask (the first version of TileLink did not have low address bits) - the dependency on addr_lo is now exposed and easy to replace
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@ -82,41 +82,48 @@ class TLWidthWidget(innerBeatBytes: Int)(implicit p: Parameters) extends LazyMod
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val inBytes = edgeIn.manager.beatBytes
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val inBytes = edgeIn.manager.beatBytes
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val outBytes = edgeOut.manager.beatBytes
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val outBytes = edgeOut.manager.beatBytes
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val ratio = inBytes / outBytes
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val ratio = inBytes / outBytes
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val keepBits = log2Ceil(inBytes)
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val dropBits = log2Ceil(outBytes)
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val countBits = log2Ceil(ratio)
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val size = edgeIn.size(in.bits)
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val hasData = edgeIn.hasData(in.bits)
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val hasData = edgeIn.hasData(in.bits)
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val size = edgeIn.size(in.bits)
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val limit = UIntToOH1(size, keepBits) >> dropBits
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val data = edgeIn.data(in.bits)
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val mask = edgeIn.mask(in.bits)
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val dataSlices = Vec.tabulate(ratio) { i => data((i+1)*outBytes*8-1, i*outBytes*8) }
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val count = RegInit(UInt(0, width = countBits))
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val maskSlices = Vec.tabulate(ratio) { i => mask((i+1)*outBytes -1, i*outBytes) }
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val first = count === UInt(0)
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val filter = Reg(UInt(width = ratio), init = SInt(-1, width = ratio).asUInt)
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val last = count === limit || !hasData
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val maskR = maskSlices.map(_.orR)
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// decoded_size = 1111 (for smallest), 0101, 0001 (for largest)
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val sizeOH1 = UIntToOH1(size, log2Ceil(inBytes)) >> log2Ceil(outBytes)
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val decoded_size = Seq.tabulate(ratio) { i => trailingZeros(i).map(!sizeOH1(_)).getOrElse(Bool(true)) }
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val first = filter(ratio-1)
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val new_filter = Mux(first, Cat(decoded_size.reverse), filter << 1)
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val last = new_filter(ratio-1) || !hasData
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when (out.fire()) {
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when (out.fire()) {
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filter := new_filter
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count := count + UInt(1)
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when (!hasData) { filter := SInt(-1, width = ratio).asUInt }
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when (last) { count := UInt(0) }
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}
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}
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val select = Cat(maskR.reverse) & new_filter
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// For sub-beat transfer, extract which part matters
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val dataOut = if (edgeIn.staticHasData(in.bits) == Some(false)) UInt(0) else Mux1H(select, dataSlices)
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val sel = in.bits match {
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val maskOut = Mux1H(select, maskSlices)
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case a: TLBundleA => a.address(keepBits-1, dropBits)
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case b: TLBundleB => b.address(keepBits-1, dropBits)
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case c: TLBundleC => c.address(keepBits-1, dropBits)
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case d: TLBundleD => d.addr_lo(keepBits-1, dropBits)
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}
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val index = sel | count
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def helper(idata: UInt, width: Int): UInt = {
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val mux = Vec.tabulate(ratio) { i => idata((i+1)*outBytes*width-1, i*outBytes*width) }
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mux(index)
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}
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out <> in
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out <> in
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edgeOut.data(out.bits) := dataOut
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out.bits match {
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// Don't put down hardware if we never carry data
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case a: TLBundleA => a.mask := maskOut
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edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) UInt(0) else helper(edgeIn.data(in.bits), 8))
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case b: TLBundleB => b.mask := maskOut
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case c: TLBundleC => ()
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(out.bits, in.bits) match {
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case d: TLBundleD => () // addr_lo gets truncated automagically
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case (o: TLBundleA, i: TLBundleA) => o.mask := helper(i.mask, 1)
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case (o: TLBundleB, i: TLBundleB) => o.mask := helper(i.mask, 1)
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case (o: TLBundleC, i: TLBundleC) => () // error handled by bulk connect
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case (o: TLBundleD, i: TLBundleD) => () // error handled by bulk connect
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case _ => require(false, "Impossbile bundle combination in WidthWidget")
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}
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}
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// Repeat the input if we're not last
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// Repeat the input if we're not last
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@ -150,9 +157,7 @@ class TLWidthWidget(innerBeatBytes: Int)(implicit p: Parameters) extends LazyMod
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if (edgeOut.manager.anySupportAcquireB && edgeIn.client.anySupportProbe) {
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if (edgeOut.manager.anySupportAcquireB && edgeIn.client.anySupportProbe) {
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splice(edgeOut, out.b, edgeIn, in.b)
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splice(edgeOut, out.b, edgeIn, in.b)
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splice(edgeIn, in.c, edgeOut, out.c)
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splice(edgeIn, in.c, edgeOut, out.c)
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in.e.ready := out.e.ready
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out.e <> in.e
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out.e.valid := in.e.valid
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out.e.bits := in.e.bits
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} else {
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} else {
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in.b.valid := Bool(false)
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in.b.valid := Bool(false)
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in.c.ready := Bool(true)
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in.c.ready := Bool(true)
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