Write test harness in Chisel

This is an unavoidably invasive commit, because it affects the unit tests
(which formerly exited using stop()), the test harness Verilog generator
(since it is no longer necessary), and the DRAM model (since it is no
longer connected).  However, this should substantially reduce the effort
of building test harnesses in the future, since manual or semi-automatic
Verilog writing should no longer be necessary.  Furthermore, there is now
very little duplication of effort between the Verilator and VCS test
harnesses.

This commit removes support for DRAMsim, which is a bit of an unfortunate
consequence.  The main blocker is the lack of Verilog parameterization for
BlackBox.  It would be straightforward to revive DRAMsim once support for
that feature is added to Chisel and FIRRTL.  But that might not even be
necessary, as we move towards synthesizable DRAM models and FAME-1
transformations.

coreplex/src/main/scala/Coreplex.scala

@@ -228,18 +228,19 @@ class DefaultOuterMemorySystem(implicit p: Parameters) extends OuterMemorySystem
   io.mem <> mem_ic.io.out
 }
 
-class CoreplexIO(implicit val p: Parameters) extends ParameterizedBundle()(p)
-    with HasCoreplexParameters {
-  val mem  = Vec(nMemChannels, new ClientUncachedTileLinkIO()(outermostParams))
-  val bus = if (p(ExportBusPort)) Some(new ClientUncachedTileLinkIO()(innerParams).flip) else None
-  val mmio = if(p(ExportMMIOPort)) Some(new ClientUncachedTileLinkIO()(outermostMMIOParams)) else None
-  val interrupts = Vec(p(NExtInterrupts), Bool()).asInput
-  val debug = new DebugBusIO()(p).flip
-  val extra = p(ExtraCoreplexPorts)(p)
-}
-
 abstract class Coreplex(implicit val p: Parameters) extends Module
     with HasCoreplexParameters {
+  class CoreplexIO(implicit val p: Parameters) extends Bundle {
+    val mem  = Vec(nMemChannels, new ClientUncachedTileLinkIO()(outermostParams))
+    val bus = if (p(ExportBusPort)) Some(new ClientUncachedTileLinkIO()(innerParams).flip) else None
+    val mmio = if(p(ExportMMIOPort)) Some(new ClientUncachedTileLinkIO()(outermostMMIOParams)) else None
+    val interrupts = Vec(p(NExtInterrupts), Bool()).asInput
+    val debug = new DebugBusIO()(p).flip
+    val extra = p(ExtraCoreplexPorts)(p)
+    val success: Option[Bool] = if (hasSuccessFlag) Some(Bool(OUTPUT)) else None
+  }
+
+  def hasSuccessFlag: Boolean = false
   val io = new CoreplexIO
 }
 
@@ -276,3 +277,8 @@ class DefaultCoreplex(topParams: Parameters) extends Coreplex()(topParams) {
   if (exportMMIO) { io.mmio.get <> uncore.io.mmio.get }
   io.mem <> uncore.io.mem
 }
+
+class GroundTestCoreplex(topParams: Parameters) extends DefaultCoreplex(topParams) {
+  override def hasSuccessFlag = true
+  io.success.get := tileList.flatMap(_.io.elements get "success").map(_.asInstanceOf[Bool]).reduce(_&&_)
+}

coreplex/src/main/scala/DirectGroundTest.scala

@@ -9,7 +9,6 @@ import uncore.agents._
 case object ExportGroundTestStatus extends Field[Boolean]
 
 class DirectGroundTestCoreplex(topParams: Parameters) extends Coreplex()(topParams) {
-
   // Not using the debug 
   io.debug.req.ready := Bool(false)
   io.debug.resp.valid := Bool(false)
@@ -27,8 +26,6 @@ class DirectGroundTestCoreplex(topParams: Parameters) extends Coreplex()(topPara
   require(test.io.mem.size == nBanksPerMemChannel)
   require(test.io.ptw.size == 0)
 
-  when (test.io.status.finished) { stop() }
-
   val mem_ic = Module(new TileLinkMemoryInterconnect(
     nBanksPerMemChannel, nMemChannels)(outermostParams))
 
@@ -59,4 +56,7 @@ class DirectGroundTestCoreplex(topParams: Parameters) extends Coreplex()(topPara
     status.timeout.valid := (state === s_timeout)
     status.timeout.bits := timeout_code
   }
+
+  override def hasSuccessFlag = true
+  io.success.get := test.io.status.finished
 }

coreplex/src/main/scala/TestConfigs.scala

@@ -15,51 +15,6 @@ import cde.{Parameters, Config, Dump, Knob, CDEMatchError}
 import scala.math.max
 import ConfigUtils._
 
-class WithGroundTest extends Config(
-  (pname, site, here) => pname match {
-    case TLKey("L1toL2") => {
-      val useMEI = site(NTiles) <= 1 && site(NCachedTileLinkPorts) <= 1
-      TileLinkParameters(
-        coherencePolicy = (
-          if (useMEI) new MEICoherence(site(L2DirectoryRepresentation))
-          else new MESICoherence(site(L2DirectoryRepresentation))),
-        nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels) + 1,
-        nCachingClients = site(NCachedTileLinkPorts),
-        nCachelessClients = site(NUncachedTileLinkPorts),
-        maxClientXacts = ((site(NMSHRs) + 1) +:
-                           site(GroundTestKey).map(_.maxXacts))
-                             .reduce(max(_, _)),
-        maxClientsPerPort = 1,
-        maxManagerXacts = site(NAcquireTransactors) + 2,
-        dataBeats = 8,
-        dataBits = site(CacheBlockBytes)*8)
-    }
-    case BuildTiles => {
-      val groundtest = if (site(XLen) == 64)
-        DefaultTestSuites.groundtest64
-      else
-        DefaultTestSuites.groundtest32
-      TestGeneration.addSuite(groundtest("p"))
-      TestGeneration.addSuite(DefaultTestSuites.emptyBmarks)
-      (0 until site(NTiles)).map { i =>
-        val tileSettings = site(GroundTestKey)(i)
-        (r: Bool, p: Parameters) => {
-          Module(new GroundTestTile(resetSignal = r)(p.alterPartial({
-            case TLId => "L1toL2"
-            case GroundTestId => i
-            case NCachedTileLinkPorts => if(tileSettings.cached > 0) 1 else 0
-            case NUncachedTileLinkPorts => tileSettings.uncached
-          })))
-        }
-      }
-    }
-    case UseFPU => false
-    case UseAtomics => false
-    case UseCompressed => false
-    case RegressionTestNames => LinkedHashSet("rv64ui-p-simple")
-    case _ => throw new CDEMatchError
-  })
-
 class WithComparator extends Config(
   (pname, site, here) => pname match {
     case GroundTestKey => Seq.fill(site(NTiles)) {

coreplex/src/main/scala/UnitTest.scala

@@ -16,5 +16,7 @@ class UnitTestCoreplex(topParams: Parameters) extends Coreplex()(topParams) {
 
   val l1params = p.alterPartial({ case TLId => "L1toL2" })
   val tests = Module(new UnitTestSuite()(l1params))
-  when (tests.io.finished) { stop() }
+
+  override def hasSuccessFlag = true
+  io.success.get := tests.io.finished
 }