riscv/rocket-chip
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Refactored coherence better from uncore hub, better coherence function names

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This commit is contained in:
Henry Cook
2012-04-03 12:03:05 -07:00
parent aee9378712
commit ed79ec98f7
5 changed files with 603 additions and 577 deletions
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21
rocket/src/main/scala/consts.scala
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@ -198,30 +198,9 @@ object Constants
val NGLOBAL_XACTS = 1 << GLOBAL_XACT_ID_BITS
val X_INIT_TYPE_BITS = 2
val X_INIT_READ_SHARED = UFix(0, X_INIT_TYPE_BITS)
val X_INIT_READ_EXCLUSIVE = UFix(1, X_INIT_TYPE_BITS)
val X_INIT_READ_UNCACHED = UFix(2, X_INIT_TYPE_BITS)
val X_INIT_WRITE_UNCACHED = UFix(3, X_INIT_TYPE_BITS)
val X_REP_TYPE_BITS = 3
val X_REP_READ_SHARED = UFix(0, X_REP_TYPE_BITS)
val X_REP_READ_EXCLUSIVE = UFix(1, X_REP_TYPE_BITS)
val X_REP_READ_UNCACHED = UFix(2, X_REP_TYPE_BITS)
val X_REP_WRITE_UNCACHED = UFix(3, X_REP_TYPE_BITS)
val X_REP_READ_EXCLUSIVE_ACK = UFix(4, X_REP_TYPE_BITS)
val P_REQ_TYPE_BITS = 2
val P_REQ_INVALIDATE = UFix(0, P_REQ_TYPE_BITS)
val P_REQ_DOWNGRADE = UFix(1, P_REQ_TYPE_BITS)
val P_REQ_COPY = UFix(2, P_REQ_TYPE_BITS)
val P_REP_TYPE_BITS = 3
val P_REP_INVALIDATE_DATA = UFix(0, P_REP_TYPE_BITS)
val P_REP_DOWNGRADE_DATA = UFix(1, P_REP_TYPE_BITS)
val P_REP_COPY_DATA = UFix(2, P_REP_TYPE_BITS)
val P_REP_INVALIDATE_ACK = UFix(3, P_REP_TYPE_BITS)
val P_REP_DOWNGRADE_ACK = UFix(4, P_REP_TYPE_BITS)
val P_REP_COPY_ACK = UFix(5, P_REP_TYPE_BITS)
// external memory interface
val MEM_TAG_BITS = max(TILE_XACT_ID_BITS, GLOBAL_XACT_ID_BITS)