From ed4224dde4d899982617dbcc3fd7ccd474f5bf9e Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Mon, 31 Oct 2016 15:17:10 -0700 Subject: [PATCH] tilelink2 AtomicAutomata: fix AccessAck on same cycle as PutFull If we send out the PutFull portion of an AMO, the slave is allowed to respond with AccessAck on the same cycle. In this case, we are still in the AMO state, but must still match the D response. --- src/main/scala/uncore/tilelink2/AtomicAutomata.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/uncore/tilelink2/AtomicAutomata.scala b/src/main/scala/uncore/tilelink2/AtomicAutomata.scala index 70bacae2..1a471334 100644 --- a/src/main/scala/uncore/tilelink2/AtomicAutomata.scala +++ b/src/main/scala/uncore/tilelink2/AtomicAutomata.scala @@ -94,7 +94,7 @@ class TLAtomicAutomata(logical: Boolean = true, arithmetic: Boolean = true, conc val cam_free = cam_s.map(_.state === FREE) val cam_amo = cam_s.map(_.state === AMO) val cam_abusy = cam_s.map(e => e.state === GET || e.state === AMO) // A is blocked - val cam_dmatch = cam_s.map(e => e.state === GET || e.state === ACK) // D should inspect these entries + val cam_dmatch = cam_s.map(e => e.state =/= FREE) // D should inspect these entries // Can the manager already handle this message? val a_size = edgeIn.size(in.a.bits) @@ -211,7 +211,7 @@ class TLAtomicAutomata(logical: Boolean = true, arithmetic: Boolean = true, conc val d_cam_sel_match = (d_cam_sel_raw zip cam_dmatch) map { case (a,b) => a&&b } val d_cam_data = Mux1H(d_cam_sel_match, cam_d.map(_.data)) val d_cam_sel_bypass = if (edgeOut.manager.minLatency > 0) Bool(false) else - out.d.bits.source === in.a.bits.source && in.a.valid && out.d.valid && !a_isSupported + out.d.bits.source === in.a.bits.source && in.a.valid && !a_isSupported val d_cam_sel = (a_cam_sel_free zip d_cam_sel_match) map { case (a,d) => Mux(d_cam_sel_bypass, a, d) } val d_cam_sel_any = d_cam_sel_bypass || d_cam_sel_match.reduce(_ || _) val d_ackd = out.d.bits.opcode === TLMessages.AccessAckData