tilelink2 Fuzzer: work around for firrtl/verilator performance issue
Big Vec()s cause very slow compilation.
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@ -14,23 +14,22 @@ class IDMapGenerator(numIds: Int) extends Module {
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}
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// True indicates that the id is available
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val bitmap = RegInit(Vec.fill(numIds){Bool(true)})
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val bitmap = RegInit(UInt((BigInt(1) << numIds) - 1, width = numIds))
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io.free.ready := Bool(true)
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assert (!io.free.valid || !bitmap(io.free.bits)) // No double freeing
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val mask = bitmap.scanLeft(Bool(false))(_||_).init
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val select = mask zip bitmap map { case(m,b) => !m && b }
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val select = ~(highOR(bitmap) << 1) & bitmap
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io.alloc.bits := OHToUInt(select)
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io.alloc.valid := bitmap.reduce(_||_)
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io.alloc.valid := bitmap.orR()
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when (io.alloc.fire()) {
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bitmap(io.alloc.bits) := Bool(false)
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}
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val clr = Wire(init = UInt(0, width = numIds))
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when (io.alloc.fire()) { clr := UIntToOH(io.alloc.bits) }
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when (io.free.fire()) {
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bitmap(io.free.bits) := Bool(true)
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}
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val set = Wire(init = UInt(0, width = numIds))
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when (io.free.fire()) { set := UIntToOH(io.free.bits) }
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bitmap := (bitmap & ~clr) | set
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}
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object LFSR64
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@ -10,6 +10,12 @@ package object tilelink2
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def OH1ToUInt(x: UInt) = OHToUInt((x << 1 | UInt(1)) ^ x)
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def UIntToOH1(x: UInt, width: Int) = ~(SInt(-1, width=width).asUInt << x)(width-1, 0)
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def trailingZeros(x: Int) = if (x > 0) Some(log2Ceil(x & -x)) else None
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def highOR(x: UInt) = {
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val w = x.getWidth
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def helper(s: Int, x: UInt): UInt =
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if (s >= w) x else helper(s+s, x | x << s)
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helper(1, x)
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}
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def sourceLine(sourceInfo: SourceInfo, prefix: String = " (", suffix: String = ")") = sourceInfo match {
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case SourceLine(filename, line, col) => s"$prefix$filename:$line:$col$suffix"
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