Refactor AddrMap and its usage (#122)
This commit is contained in:
Andrew Waterman
parent
c8338ad809
commit
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Subproject commit f44383cd9b12cc1f58a5e4a278e3e3b65d34346d
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Subproject commit 278bcb1b7086391a984aa4331d66cd2146f12b5d
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Subproject commit bf5823a6ed211b489359a13697d7db726bcbb123
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Subproject commit 4562d3c98eb677f2aea47692e02006efcf260800
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rocket
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rocket
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Subproject commit ae6ac02c758f14fd594e5707125ae931ea530d75
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Subproject commit b42ff4233d0d3800c7e5c87de62ed97f0c074336
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@ -25,35 +25,34 @@ class BaseConfig extends Config (
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def findBy(sname:Any):Any = here[PF](site[Any](sname))(pname)
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lazy val internalIOAddrMap: AddrMap = {
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val entries = collection.mutable.ArrayBuffer[AddrMapEntry]()
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entries += AddrMapEntry("debug", MemSize(1<<12, 1<<12, MemAttr(AddrMapProt.RWX)))
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entries += AddrMapEntry("bootrom", MemSize(1<<12, 1<<12, MemAttr(AddrMapProt.RX)))
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entries += AddrMapEntry("rtc", MemSize(1<<12, 1<<12, MemAttr(AddrMapProt.RW)))
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entries += AddrMapEntry("debug", MemSize(4096, MemAttr(AddrMapProt.RWX)))
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entries += AddrMapEntry("bootrom", MemSize(4096, MemAttr(AddrMapProt.RX)))
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entries += AddrMapEntry("rtc", MemSize(4096, MemAttr(AddrMapProt.RW)))
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entries += AddrMapEntry("plic", MemRange(0x40000000, 4096 * 1024, MemAttr(AddrMapProt.RW)))
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for (i <- 0 until site(NTiles))
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entries += AddrMapEntry(s"prci$i", MemSize(1<<12, 1<<12, MemAttr(AddrMapProt.RW)))
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entries += AddrMapEntry("plic", MemSize(1<<22, 1<<22, MemAttr(AddrMapProt.RW)))
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entries += AddrMapEntry(s"prci$i", MemSize(4096, MemAttr(AddrMapProt.RW)))
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new AddrMap(entries)
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}
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lazy val (globalAddrMap, globalAddrHashMap) = {
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val memSize = 1L << 31
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val memAlign = 1L << 30
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val extIOSize = 1L << 30
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val mem = MemSize(memSize, memAlign, MemAttr(AddrMapProt.RWX, true))
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lazy val globalAddrMap = {
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val memBase = 0x80000000L
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val memSize = 0x80000000L
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val extIOBase = 0x60000000L
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val extIOSize = 0x20000000L
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val io = AddrMap(
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AddrMapEntry("int", MemSubmap(internalIOAddrMap.computeSize, internalIOAddrMap)),
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AddrMapEntry("ext", MemSize(extIOSize, extIOSize, MemAttr(AddrMapProt.RWX))))
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AddrMapEntry("int", internalIOAddrMap),
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AddrMapEntry("ext", MemRange(extIOBase, extIOSize, MemAttr(AddrMapProt.RWX))))
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val addrMap = AddrMap(
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AddrMapEntry("io", MemSubmap(io.computeSize, io)),
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AddrMapEntry("mem", mem))
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AddrMapEntry("io", io),
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AddrMapEntry("mem", MemRange(memBase, memSize, MemAttr(AddrMapProt.RWX, true))))
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val addrHashMap = new AddrHashMap(addrMap)
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Dump("MEM_BASE", addrHashMap("mem").start)
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Dump("MEM_BASE", addrMap("mem").start)
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Dump("MEM_SIZE", memSize)
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Dump("IO_BASE", addrHashMap("io:ext").start)
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Dump("IO_BASE", addrMap("io:ext").start)
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Dump("IO_SIZE", extIOSize)
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(addrMap, addrHashMap)
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addrMap
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}
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def makeConfigString() = {
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val addrMap = globalAddrHashMap
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val addrMap = globalAddrMap
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val plicAddr = addrMap(s"io:int:plic").start
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val plicInfo = site(PLICKey)
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val xLen = site(XLen)
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@ -73,7 +72,7 @@ class BaseConfig extends Config (
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res append "ram {\n"
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res append " 0 {\n"
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res append s" addr 0x${addrMap("mem").start.toString(16)};\n"
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res append s" size 0x${addrMap("mem").region.size.toString(16)};\n"
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res append s" size 0x${addrMap("mem").size.toString(16)};\n"
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res append " };\n"
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res append "};\n"
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res append "core {\n"
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@ -224,7 +223,7 @@ class BaseConfig extends Config (
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}
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case NExtInterrupts => 2
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case NExtMMIOChannels => 0
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case PLICKey => PLICConfig(site(NTiles), site(UseVM), site(NExtInterrupts), site(NExtInterrupts))
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case PLICKey => PLICConfig(site(NTiles), site(UseVM), site(NExtInterrupts), 0)
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case DMKey => new DefaultDebugModuleConfig(site(NTiles), site(XLen))
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case FDivSqrt => true
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case SFMALatency => 2
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@ -281,11 +280,10 @@ class BaseConfig extends Config (
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maxClientsPerPort = site(NBanksPerMemoryChannel),
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dataBeats = site(MIFDataBeats))
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case TLKey("L2toMMIO") => {
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val addrMap = globalAddrHashMap
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TileLinkParameters(
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coherencePolicy = new MICoherence(
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new NullRepresentation(site(NBanksPerMemoryChannel))),
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nManagers = addrMap.nEntries - 1,
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nManagers = globalAddrMap.subMap("io").flatten.size,
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nCachingClients = 0,
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nCachelessClients = 1,
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maxClientXacts = 4,
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@ -305,7 +303,6 @@ class BaseConfig extends Config (
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case UseHtifClockDiv => true
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case ConfigString => makeConfigString()
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case GlobalAddrMap => globalAddrMap
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case GlobalAddrHashMap => globalAddrHashMap
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case _ => throw new CDEMatchError
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}},
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knobValues = {
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@ -19,16 +19,13 @@ class DeviceSet {
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def addDevice(dev: Device): Unit =
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deviceMap(dev.name) = dev
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private def roundup(size: Int): Int = (1 << log2Ceil(size))
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def toSeq: Seq[Device] = deviceMap.values.toSeq
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def getAddrMap: AddrMap = {
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val devices = this.toSeq.sortWith((a, b) => a.size > b.size)
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val entries = devices.map { case Device(name, size, _, readable, writeable) =>
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val prot = (if (readable) AddrMapProt.R else 0) | (if (writeable) AddrMapProt.W else 0)
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val realsize = roundup(size)
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AddrMapEntry(name, MemSize(size, roundup(size), MemAttr(prot)))
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AddrMapEntry(name, MemSize(size, MemAttr(prot)))
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}
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new AddrMap(entries)
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}
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@ -104,8 +104,7 @@ object TopUtils {
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rom.order(java.nio.ByteOrder.LITTLE_ENDIAN)
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// for now, have the reset vector jump straight to memory
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val addrHashMap = p(GlobalAddrHashMap)
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val resetToMemDist = addrHashMap("mem").start - p(ResetVector)
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val resetToMemDist = p(GlobalAddrMap)("mem").start - p(ResetVector)
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require(resetToMemDist == (resetToMemDist.toInt >> 12 << 12))
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val configStringAddr = p(ResetVector).toInt + rom.capacity
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@ -174,8 +173,6 @@ class Uncore(implicit val p: Parameters) extends Module
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outmemsys.io.tiles_uncached <> io.tiles_uncached
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outmemsys.io.tiles_cached <> io.tiles_cached
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val addrMap = p(GlobalAddrMap)
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val addrHashMap = p(GlobalAddrHashMap)
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val scrFile = Module(new SCRFile("UNCORE_SCR", 0))
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scrFile.io.smi <> htif.io.scr
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// scrFile.io.scr <> (... your SCR connections ...)
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@ -194,20 +191,16 @@ class Uncore(implicit val p: Parameters) extends Module
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htif.io.cpu.foreach { _.csr.resp.valid := Bool(false) }
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def buildMMIONetwork(implicit p: Parameters) = {
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val (ioBase, ioAddrMap) = addrHashMap.subMap("io")
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val ioAddrHashMap = new AddrHashMap(ioAddrMap, ioBase)
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val ioAddrMap = p(GlobalAddrMap).subMap("io")
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val mmioNetwork = Module(new TileLinkRecursiveInterconnect(1, ioAddrMap, ioBase))
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val mmioNetwork = Module(new TileLinkRecursiveInterconnect(1, ioAddrMap))
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TileLinkWidthAdapter(outmemsys.io.mmio, mmioNetwork.io.in.head)
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val rtc = Module(new RTC(p(NTiles)))
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val rtcAddr = ioAddrHashMap("int:rtc")
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require(rtc.size <= rtcAddr.region.size)
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rtc.io.tl <> mmioNetwork.io.out(rtcAddr.port)
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rtc.io.tl <> mmioNetwork.port("int:rtc")
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val plic = Module(new PLIC(p(PLICKey)))
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val plicAddr = ioAddrHashMap("int:plic")
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plic.io.tl <> mmioNetwork.io.out(plicAddr.port)
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plic.io.tl <> mmioNetwork.port("int:plic")
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for (i <- 0 until io.interrupts.size) {
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val gateway = Module(new LevelGateway)
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gateway.io.interrupt := io.interrupts(i)
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@ -215,14 +208,12 @@ class Uncore(implicit val p: Parameters) extends Module
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}
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val debugModule = Module(new DebugModule)
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val debugModuleAddr = ioAddrHashMap("int:debug")
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debugModule.io.tl <> mmioNetwork.io.out(debugModuleAddr.port)
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debugModule.io.tl <> mmioNetwork.port("int:debug")
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debugModule.io.db <> io.debugBus
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for (i <- 0 until nTiles) {
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val prci = Module(new PRCI)
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val prciAddr = ioAddrHashMap(s"int:prci$i")
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prci.io.tl <> mmioNetwork.io.out(prciAddr.port)
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prci.io.tl <> mmioNetwork.port(s"int:prci$i")
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prci.io.id := UInt(i)
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prci.io.interrupts.mtip := rtc.io.irqs(i)
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@ -236,15 +227,14 @@ class Uncore(implicit val p: Parameters) extends Module
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}
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val bootROM = Module(new ROMSlave(TopUtils.makeBootROM()))
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val bootROMAddr = ioAddrHashMap("int:bootrom")
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bootROM.io <> mmioNetwork.io.out(bootROMAddr.port)
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bootROM.io <> mmioNetwork.port("int:bootrom")
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val mmioEndpoint = p(NExtMMIOChannels) match {
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case 0 => Module(new NastiErrorSlave).io
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case 1 => io.mmio(0)
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// The memory map presently has only one external I/O region
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}
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TopUtils.connectTilelinkNasti(mmioEndpoint, mmioNetwork.io.out(ioAddrHashMap("ext").port))
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TopUtils.connectTilelinkNasti(mmioEndpoint, mmioNetwork.port("ext"))
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}
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}
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@ -261,14 +251,12 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
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val mmio = new ClientUncachedTileLinkIO()(p.alterPartial({case TLId => "L2toMMIO"}))
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}
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val addrHashMap = p(GlobalAddrHashMap)
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// Create a simple L1toL2 NoC between the tiles+htif and the banks of outer memory
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// Cached ports are first in client list, making sharerToClientId just an indentity function
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// addrToBank is sed to hash physical addresses (of cache blocks) to banks (and thereby memory channels)
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def sharerToClientId(sharerId: UInt) = sharerId
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def addrToBank(addr: UInt): UInt = {
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val isMemory = addrHashMap.isInRegion("mem", addr << log2Up(p(CacheBlockBytes)))
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val isMemory = p(GlobalAddrMap).isInRegion("mem", addr << log2Up(p(CacheBlockBytes)))
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Mux(isMemory,
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if (nBanks > 1) addr(lsb + log2Up(nBanks) - 1, lsb) else UInt(0),
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UInt(nBanks))
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@ -300,8 +288,8 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
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// TODO: the code to print this stuff should live somewhere else
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println("Generated Address Map")
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for ((name, base, region) <- addrHashMap.sortedEntries) {
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println(f"\t$name%s $base%x - ${base + region.size - 1}%x")
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for ((name, region) <- p(GlobalAddrMap).flatten) {
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println(f"\t$name%s ${region.start}%x - ${region.start + region.size - 1}%x")
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}
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println("Generated Configuration String")
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println(new String(p(ConfigString)))
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@ -53,7 +53,7 @@ class WithMemtest extends Config(
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case GenerateUncached => true
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case GenerateCached => true
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case MaxGenerateRequests => 128
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case GeneratorStartAddress => site(GlobalAddrHashMap)("mem").start
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case GeneratorStartAddress => site(GlobalAddrMap)("mem").start
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case BuildGroundTest =>
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(id: Int, p: Parameters) => Module(new GeneratorTest(id)(p))
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case _ => throw new CDEMatchError
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2
uncore
2
uncore
@ -1 +1 @@
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Subproject commit b04524d2593806e8deed8f253e4e8fe9eac0c495
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Subproject commit 65db9e3eaa174bce72346770d91fe0592f964cb8
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