Refactor AddrMap and its usage (#122)

groundtest

@@ -1 +1 @@
-Subproject commit f44383cd9b12cc1f58a5e4a278e3e3b65d34346d
+Subproject commit 278bcb1b7086391a984aa4331d66cd2146f12b5d

junctions

@@ -1 +1 @@
-Subproject commit bf5823a6ed211b489359a13697d7db726bcbb123
+Subproject commit 4562d3c98eb677f2aea47692e02006efcf260800

rocket

@@ -1 +1 @@
-Subproject commit ae6ac02c758f14fd594e5707125ae931ea530d75
+Subproject commit b42ff4233d0d3800c7e5c87de62ed97f0c074336

src/main/scala/Configs.scala

@@ -25,35 +25,34 @@ class BaseConfig extends Config (
     def findBy(sname:Any):Any = here[PF](site[Any](sname))(pname)
     lazy val internalIOAddrMap: AddrMap = {
       val entries = collection.mutable.ArrayBuffer[AddrMapEntry]()
-      entries += AddrMapEntry("debug", MemSize(1<<12, 1<<12, MemAttr(AddrMapProt.RWX)))
+      entries += AddrMapEntry("debug", MemSize(4096, MemAttr(AddrMapProt.RWX)))
-      entries += AddrMapEntry("bootrom", MemSize(1<<12, 1<<12, MemAttr(AddrMapProt.RX)))
+      entries += AddrMapEntry("bootrom", MemSize(4096, MemAttr(AddrMapProt.RX)))
-      entries += AddrMapEntry("rtc", MemSize(1<<12, 1<<12, MemAttr(AddrMapProt.RW)))
+      entries += AddrMapEntry("rtc", MemSize(4096, MemAttr(AddrMapProt.RW)))
+      entries += AddrMapEntry("plic", MemRange(0x40000000, 4096 * 1024, MemAttr(AddrMapProt.RW)))
       for (i <- 0 until site(NTiles))
-        entries += AddrMapEntry(s"prci$i", MemSize(1<<12, 1<<12, MemAttr(AddrMapProt.RW)))
+        entries += AddrMapEntry(s"prci$i", MemSize(4096, MemAttr(AddrMapProt.RW)))
-      entries += AddrMapEntry("plic", MemSize(1<<22, 1<<22, MemAttr(AddrMapProt.RW)))
       new AddrMap(entries)
     }
-    lazy val (globalAddrMap, globalAddrHashMap) = {
+    lazy val globalAddrMap = {
-      val memSize = 1L << 31
+      val memBase = 0x80000000L
-      val memAlign = 1L << 30
+      val memSize = 0x80000000L
-      val extIOSize = 1L << 30
+      val extIOBase = 0x60000000L
-      val mem = MemSize(memSize, memAlign, MemAttr(AddrMapProt.RWX, true))
+      val extIOSize = 0x20000000L
       val io = AddrMap(
-        AddrMapEntry("int", MemSubmap(internalIOAddrMap.computeSize, internalIOAddrMap)),
+        AddrMapEntry("int", internalIOAddrMap),
-        AddrMapEntry("ext", MemSize(extIOSize, extIOSize, MemAttr(AddrMapProt.RWX))))
+        AddrMapEntry("ext", MemRange(extIOBase, extIOSize, MemAttr(AddrMapProt.RWX))))
       val addrMap = AddrMap(
-        AddrMapEntry("io", MemSubmap(io.computeSize, io)),
+        AddrMapEntry("io", io),
-        AddrMapEntry("mem", mem))
+        AddrMapEntry("mem", MemRange(memBase, memSize, MemAttr(AddrMapProt.RWX, true))))
 
-      val addrHashMap = new AddrHashMap(addrMap)
+      Dump("MEM_BASE", addrMap("mem").start)
-      Dump("MEM_BASE", addrHashMap("mem").start)
       Dump("MEM_SIZE", memSize)
-      Dump("IO_BASE", addrHashMap("io:ext").start)
+      Dump("IO_BASE", addrMap("io:ext").start)
       Dump("IO_SIZE", extIOSize)
-      (addrMap, addrHashMap)
+      addrMap
     }
     def makeConfigString() = {
-      val addrMap = globalAddrHashMap
+      val addrMap = globalAddrMap
       val plicAddr = addrMap(s"io:int:plic").start
       val plicInfo = site(PLICKey)
       val xLen = site(XLen)
@@ -73,7 +72,7 @@ class BaseConfig extends Config (
       res append  "ram {\n"
       res append  "  0 {\n"
       res append s"    addr 0x${addrMap("mem").start.toString(16)};\n"
-      res append s"    size 0x${addrMap("mem").region.size.toString(16)};\n"
+      res append s"    size 0x${addrMap("mem").size.toString(16)};\n"
       res append  "  };\n"
       res append  "};\n"
       res append  "core {\n"
@@ -224,7 +223,7 @@ class BaseConfig extends Config (
       }
       case NExtInterrupts => 2
       case NExtMMIOChannels => 0
-      case PLICKey => PLICConfig(site(NTiles), site(UseVM), site(NExtInterrupts), site(NExtInterrupts))
+      case PLICKey => PLICConfig(site(NTiles), site(UseVM), site(NExtInterrupts), 0)
       case DMKey => new DefaultDebugModuleConfig(site(NTiles), site(XLen))
       case FDivSqrt => true
       case SFMALatency => 2
@@ -281,11 +280,10 @@ class BaseConfig extends Config (
         maxClientsPerPort = site(NBanksPerMemoryChannel),
         dataBeats = site(MIFDataBeats))
       case TLKey("L2toMMIO") => {
-        val addrMap = globalAddrHashMap
         TileLinkParameters(
           coherencePolicy = new MICoherence(
             new NullRepresentation(site(NBanksPerMemoryChannel))),
-          nManagers = addrMap.nEntries - 1,
+          nManagers = globalAddrMap.subMap("io").flatten.size,
           nCachingClients = 0,
           nCachelessClients = 1,
           maxClientXacts = 4,
@@ -305,7 +303,6 @@ class BaseConfig extends Config (
       case UseHtifClockDiv => true
       case ConfigString => makeConfigString()
       case GlobalAddrMap => globalAddrMap
-      case GlobalAddrHashMap => globalAddrHashMap
       case _ => throw new CDEMatchError
   }},
   knobValues = {

src/main/scala/DeviceSet.scala

@@ -19,16 +19,13 @@ class DeviceSet {
   def addDevice(dev: Device): Unit =
     deviceMap(dev.name) = dev
 
-  private def roundup(size: Int): Int = (1 << log2Ceil(size))
-
   def toSeq: Seq[Device] = deviceMap.values.toSeq
 
   def getAddrMap: AddrMap = {
     val devices = this.toSeq.sortWith((a, b) => a.size > b.size)
     val entries = devices.map { case Device(name, size, _, readable, writeable) =>
       val prot = (if (readable) AddrMapProt.R else 0) | (if (writeable) AddrMapProt.W else 0)
-      val realsize = roundup(size)
+      AddrMapEntry(name, MemSize(size, MemAttr(prot)))
-      AddrMapEntry(name, MemSize(size, roundup(size), MemAttr(prot)))
     }
     new AddrMap(entries)
   }

src/main/scala/RocketChip.scala

@@ -104,8 +104,7 @@ object TopUtils {
     rom.order(java.nio.ByteOrder.LITTLE_ENDIAN)
 
     // for now, have the reset vector jump straight to memory
-    val addrHashMap = p(GlobalAddrHashMap)
+    val resetToMemDist = p(GlobalAddrMap)("mem").start - p(ResetVector)
-    val resetToMemDist = addrHashMap("mem").start - p(ResetVector)
     require(resetToMemDist == (resetToMemDist.toInt >> 12 << 12))
     val configStringAddr = p(ResetVector).toInt + rom.capacity
 
@@ -174,8 +173,6 @@ class Uncore(implicit val p: Parameters) extends Module
   outmemsys.io.tiles_uncached <> io.tiles_uncached
   outmemsys.io.tiles_cached <> io.tiles_cached
 
-  val addrMap = p(GlobalAddrMap)
-  val addrHashMap = p(GlobalAddrHashMap)
   val scrFile = Module(new SCRFile("UNCORE_SCR", 0))
   scrFile.io.smi <> htif.io.scr
   // scrFile.io.scr <> (... your SCR connections ...)
@@ -194,20 +191,16 @@ class Uncore(implicit val p: Parameters) extends Module
   htif.io.cpu.foreach { _.csr.resp.valid := Bool(false) }
 
   def buildMMIONetwork(implicit p: Parameters) = {
-    val (ioBase, ioAddrMap) = addrHashMap.subMap("io")
+    val ioAddrMap = p(GlobalAddrMap).subMap("io")
-    val ioAddrHashMap = new AddrHashMap(ioAddrMap, ioBase)
 
-    val mmioNetwork = Module(new TileLinkRecursiveInterconnect(1, ioAddrMap, ioBase))
+    val mmioNetwork = Module(new TileLinkRecursiveInterconnect(1, ioAddrMap))
     TileLinkWidthAdapter(outmemsys.io.mmio, mmioNetwork.io.in.head)
 
     val rtc = Module(new RTC(p(NTiles)))
-    val rtcAddr = ioAddrHashMap("int:rtc")
+    rtc.io.tl <> mmioNetwork.port("int:rtc")
-    require(rtc.size <= rtcAddr.region.size)
-    rtc.io.tl <> mmioNetwork.io.out(rtcAddr.port)
 
     val plic = Module(new PLIC(p(PLICKey)))
-    val plicAddr = ioAddrHashMap("int:plic")
+    plic.io.tl <> mmioNetwork.port("int:plic")
-    plic.io.tl <> mmioNetwork.io.out(plicAddr.port)
     for (i <- 0 until io.interrupts.size) {
       val gateway = Module(new LevelGateway)
       gateway.io.interrupt := io.interrupts(i)
@@ -215,14 +208,12 @@ class Uncore(implicit val p: Parameters) extends Module
     }
 
     val debugModule = Module(new DebugModule)
-    val debugModuleAddr = ioAddrHashMap("int:debug")
+    debugModule.io.tl <> mmioNetwork.port("int:debug")
-    debugModule.io.tl <> mmioNetwork.io.out(debugModuleAddr.port)
     debugModule.io.db <> io.debugBus
 
     for (i <- 0 until nTiles) {
       val prci = Module(new PRCI)
-      val prciAddr = ioAddrHashMap(s"int:prci$i")
+      prci.io.tl <> mmioNetwork.port(s"int:prci$i")
-      prci.io.tl <> mmioNetwork.io.out(prciAddr.port)
 
       prci.io.id := UInt(i)
       prci.io.interrupts.mtip := rtc.io.irqs(i)
@@ -236,15 +227,14 @@ class Uncore(implicit val p: Parameters) extends Module
     }
 
     val bootROM = Module(new ROMSlave(TopUtils.makeBootROM()))
-    val bootROMAddr = ioAddrHashMap("int:bootrom")
+    bootROM.io <> mmioNetwork.port("int:bootrom")
-    bootROM.io <> mmioNetwork.io.out(bootROMAddr.port)
 
     val mmioEndpoint = p(NExtMMIOChannels) match {
       case 0 => Module(new NastiErrorSlave).io
       case 1 => io.mmio(0)
       // The memory map presently has only one external I/O region
     }
-    TopUtils.connectTilelinkNasti(mmioEndpoint, mmioNetwork.io.out(ioAddrHashMap("ext").port))
+    TopUtils.connectTilelinkNasti(mmioEndpoint, mmioNetwork.port("ext"))
   }
 }
 
@@ -261,14 +251,12 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
     val mmio = new ClientUncachedTileLinkIO()(p.alterPartial({case TLId => "L2toMMIO"}))
   }
 
-  val addrHashMap = p(GlobalAddrHashMap)
-
   // Create a simple L1toL2 NoC between the tiles+htif and the banks of outer memory
   // Cached ports are first in client list, making sharerToClientId just an indentity function
   // addrToBank is sed to hash physical addresses (of cache blocks) to banks (and thereby memory channels)
   def sharerToClientId(sharerId: UInt) = sharerId
   def addrToBank(addr: UInt): UInt = {
-    val isMemory = addrHashMap.isInRegion("mem", addr << log2Up(p(CacheBlockBytes)))
+    val isMemory = p(GlobalAddrMap).isInRegion("mem", addr << log2Up(p(CacheBlockBytes)))
     Mux(isMemory,
       if (nBanks > 1) addr(lsb + log2Up(nBanks) - 1, lsb) else UInt(0),
       UInt(nBanks))
@@ -300,8 +288,8 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
 
   // TODO: the code to print this stuff should live somewhere else
   println("Generated Address Map")
-  for ((name, base, region) <- addrHashMap.sortedEntries) {
+  for ((name, region) <- p(GlobalAddrMap).flatten) {
-    println(f"\t$name%s $base%x - ${base + region.size - 1}%x")
+    println(f"\t$name%s ${region.start}%x - ${region.start + region.size - 1}%x")
   }
   println("Generated Configuration String")
   println(new String(p(ConfigString)))

src/main/scala/TestConfigs.scala

@@ -53,7 +53,7 @@ class WithMemtest extends Config(
     case GenerateUncached => true
     case GenerateCached => true
     case MaxGenerateRequests => 128
-    case GeneratorStartAddress => site(GlobalAddrHashMap)("mem").start
+    case GeneratorStartAddress => site(GlobalAddrMap)("mem").start
     case BuildGroundTest =>
       (id: Int, p: Parameters) => Module(new GeneratorTest(id)(p))
     case _ => throw new CDEMatchError

uncore

@@ -1 +1 @@
-Subproject commit b04524d2593806e8deed8f253e4e8fe9eac0c495
+Subproject commit 65db9e3eaa174bce72346770d91fe0592f964cb8