From ecc3c2a4b2344279983dee5ac9e031763a23d9d3 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Fri, 2 Sep 2016 11:52:47 -0700 Subject: [PATCH] tilelink2: more efficient one-hot circuits --- uncore/src/main/scala/tilelink2/Edges.scala | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/uncore/src/main/scala/tilelink2/Edges.scala b/uncore/src/main/scala/tilelink2/Edges.scala index 6fd61796..cd1a2449 100644 --- a/uncore/src/main/scala/tilelink2/Edges.scala +++ b/uncore/src/main/scala/tilelink2/Edges.scala @@ -12,8 +12,9 @@ class TLEdge( { def isAligned(address: UInt, lgSize: UInt) = if (maxLgSize == 0) Bool(true) else { - val mask = Vec.tabulate(maxLgSize) { UInt(_) < lgSize } - (address & Cat(mask.reverse)) === UInt(0) + val ones = UInt((1 << maxLgSize) - 1) + val mask = (ones << lgSize)(maxLgSize*2-1, maxLgSize) + (address & mask) === UInt(0) } // This gets used everywhere, so make the smallest circuit possible ... @@ -43,8 +44,8 @@ class TLEdge( val size = bundle.size() val cutoff = log2Ceil(manager.beatBytes) val small = size <= UInt(cutoff) - val decode = Vec.tabulate (1+maxLgSize-cutoff) { i => UInt(i + cutoff) === size } - Mux(!hasData || small, UInt(1), Cat(decode.reverse)) + val decode = UIntToOH(size, maxLgSize+1) >> cutoff + Mux(!hasData || small, UInt(1), decode) } }