diff --git a/src/main/scala/rocket/IBuf.scala b/src/main/scala/rocket/IBuf.scala
index 399b394d..f5c77d1f 100644
--- a/src/main/scala/rocket/IBuf.scala
+++ b/src/main/scala/rocket/IBuf.scala
@@ -43,24 +43,24 @@ class IBuf(implicit p: Parameters) extends CoreModule {
   val nIC = Mux(io.imem.bits.btb.valid && io.imem.bits.btb.bits.taken, io.imem.bits.btb.bits.bridx +& 1, UInt(fetchWidth)) - pcWordBits
   val nICReady = nReady - nBufValid
   val nValid = Mux(io.imem.valid, nIC, UInt(0)) + nBufValid
-  io.imem.ready := nReady >= nBufValid && (nICReady >= nIC || n >= nIC - nICReady)
+  io.imem.ready := io.inst(0).ready && nReady >= nBufValid && (nICReady >= nIC || n >= nIC - nICReady)
 
   if (n > 0) {
-    nBufValid := Mux(nReady >= nBufValid, UInt(0), nBufValid - nReady)
-    if (n > 1) when (nReady > 0 && nReady < nBufValid) {
-      val shiftedBuf = shiftInsnRight(buf.data(n*coreInstBits-1, coreInstBits), (nReady-1)(log2Ceil(n-1)-1,0))
-      buf.data := Cat(buf.data(n*coreInstBits-1, (n-1)*coreInstBits), shiftedBuf((n-1)*coreInstBits-1, 0))
-      buf.pc := buf.pc & ~pcWordMask | (buf.pc + (nReady << log2Ceil(coreInstBytes))) & pcWordMask
-      ibufBTBResp.bridx := ibufBTBResp.bridx - nReady
-    }
-    when (io.imem.valid && nReady >= nBufValid && nICReady < nIC && n >= nIC - nICReady) {
-      val shamt = pcWordBits + nICReady
-      nBufValid := nIC - nICReady
-      buf := io.imem.bits
-      buf.data := shiftInsnRight(io.imem.bits.data, shamt)(n*coreInstBits-1,0)
-      buf.pc := io.imem.bits.pc & ~pcWordMask | (io.imem.bits.pc + (nICReady << log2Ceil(coreInstBytes))) & pcWordMask
-      ibufBTBHit := io.imem.bits.btb.valid
-      when (io.imem.bits.btb.valid) {
+    when (io.inst(0).ready) {
+      nBufValid := Mux(nReady >= nBufValid, UInt(0), nBufValid - nReady)
+      if (n > 1) when (nReady > 0 && nReady < nBufValid) {
+        val shiftedBuf = shiftInsnRight(buf.data(n*coreInstBits-1, coreInstBits), (nReady-1)(log2Ceil(n-1)-1,0))
+        buf.data := Cat(buf.data(n*coreInstBits-1, (n-1)*coreInstBits), shiftedBuf((n-1)*coreInstBits-1, 0))
+        buf.pc := buf.pc & ~pcWordMask | (buf.pc + (nReady << log2Ceil(coreInstBytes))) & pcWordMask
+        ibufBTBResp.bridx := ibufBTBResp.bridx - nReady
+      }
+      when (io.imem.valid && nReady >= nBufValid && nICReady < nIC && n >= nIC - nICReady) {
+        val shamt = pcWordBits + nICReady
+        nBufValid := nIC - nICReady
+        buf := io.imem.bits
+        buf.data := shiftInsnRight(io.imem.bits.data, shamt)(n*coreInstBits-1,0)
+        buf.pc := io.imem.bits.pc & ~pcWordMask | (io.imem.bits.pc + (nICReady << log2Ceil(coreInstBytes))) & pcWordMask
+        ibufBTBHit := io.imem.bits.btb.valid
         ibufBTBResp := io.imem.bits.btb.bits
         ibufBTBResp.bridx := io.imem.bits.btb.bits.bridx + nICReady
       }
@@ -97,18 +97,19 @@ class IBuf(implicit p: Parameters) extends CoreModule {
 
     if (usingCompressed) {
       val replay = ic_replay(j) || (!exp.io.rvc && (btbHitMask(j) || ic_replay(j+1)))
-      io.inst(i).valid := valid(j) && (exp.io.rvc || valid(j+1) || xcpt(j+1).asUInt.orR || replay)
+      val full_insn = exp.io.rvc || valid(j+1) || xcpt(j+1).asUInt.orR || replay
+      io.inst(i).valid := valid(j) && full_insn
       io.inst(i).bits.xcpt0 := xcpt(j)
       io.inst(i).bits.xcpt1 := Mux(exp.io.rvc, 0.U, xcpt(j+1).asUInt).asTypeOf(new FrontendExceptions)
       io.inst(i).bits.replay := replay
       io.inst(i).bits.btb_hit := btbHitMask(j) || (!exp.io.rvc && btbHitMask(j+1))
       io.inst(i).bits.rvc := exp.io.rvc
 
-      when (io.inst(i).fire()) { nReady := Mux(exp.io.rvc, j+1, j+2) }
+      when (full_insn && (i == 0 || io.inst(i).ready)) { nReady := Mux(exp.io.rvc, j+1, j+2) }
 
       expand(i+1, Mux(exp.io.rvc, j+1, j+2), Mux(exp.io.rvc, curInst >> 16, curInst >> 32))
     } else {
-      when (io.inst(i).ready) { nReady := i+1 }
+      when (i == 0 || io.inst(i).ready) { nReady := i+1 }
       io.inst(i).valid := valid(i)
       io.inst(i).bits.xcpt0 := xcpt(i)
       io.inst(i).bits.xcpt1 := 0.U.asTypeOf(new FrontendExceptions)