From ec809483b05a1987f6f1c83280d1b1843b95efd0 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Sat, 18 Nov 2017 14:36:29 -0800 Subject: [PATCH] BusBypass: assert fail if the widths of the two slaves do not match --- .../scala/devices/tilelink/BusBypass.scala | 31 ++++++++++--------- 1 file changed, 17 insertions(+), 14 deletions(-) diff --git a/src/main/scala/devices/tilelink/BusBypass.scala b/src/main/scala/devices/tilelink/BusBypass.scala index d9784818..03989899 100644 --- a/src/main/scala/devices/tilelink/BusBypass.scala +++ b/src/main/scala/devices/tilelink/BusBypass.scala @@ -52,28 +52,31 @@ class TLBusBypassBar(implicit p: Parameters) extends LazyModule val pending = Bool(OUTPUT) }) - val (in, edge) = node.in(0) - val Seq((out0,_), (out1,_)) = node.out + val (in, edgeIn) = node.in(0) + val Seq((out0, edgeOut0), (out1, edgeOut1)) = node.out - val bce = edge.manager.anySupportAcquireB && edge.client.anySupportProbe + require (edgeOut0.manager.beatBytes == edgeOut1.manager.beatBytes, + s"BusBypass slave device widths mismatch (${edgeOut0.manager.managers.map(_.name)} has ${edgeOut0.manager.beatBytes}B vs ${edgeOut1.manager.managers.map(_.name)} has ${edgeOut1.manager.beatBytes}B)") + + val bce = edgeIn.manager.anySupportAcquireB && edgeIn.client.anySupportProbe // We need to be locked to the given bypass direction until all transactions stop - val flight = RegInit(UInt(0, width = log2Ceil(3*edge.client.endSourceId+1))) + val flight = RegInit(UInt(0, width = log2Ceil(3*edgeIn.client.endSourceId+1))) val bypass = RegInit(io.bypass) // synchronous reset required io.pending := (flight > 0.U) - val (a_first, a_last, _) = edge.firstlast(in.a) - val (b_first, b_last, _) = edge.firstlast(in.b) - val (c_first, c_last, _) = edge.firstlast(in.c) - val (d_first, d_last, _) = edge.firstlast(in.d) - val (e_first, e_last, _) = edge.firstlast(in.e) + val (a_first, a_last, _) = edgeIn.firstlast(in.a) + val (b_first, b_last, _) = edgeIn.firstlast(in.b) + val (c_first, c_last, _) = edgeIn.firstlast(in.c) + val (d_first, d_last, _) = edgeIn.firstlast(in.d) + val (e_first, e_last, _) = edgeIn.firstlast(in.e) - val (a_request, a_response) = (edge.isRequest(in.a.bits), edge.isResponse(in.a.bits)) - val (b_request, b_response) = (edge.isRequest(in.b.bits), edge.isResponse(in.b.bits)) - val (c_request, c_response) = (edge.isRequest(in.c.bits), edge.isResponse(in.c.bits)) - val (d_request, d_response) = (edge.isRequest(in.d.bits), edge.isResponse(in.d.bits)) - val (e_request, e_response) = (edge.isRequest(in.e.bits), edge.isResponse(in.e.bits)) + val (a_request, a_response) = (edgeIn.isRequest(in.a.bits), edgeIn.isResponse(in.a.bits)) + val (b_request, b_response) = (edgeIn.isRequest(in.b.bits), edgeIn.isResponse(in.b.bits)) + val (c_request, c_response) = (edgeIn.isRequest(in.c.bits), edgeIn.isResponse(in.c.bits)) + val (d_request, d_response) = (edgeIn.isRequest(in.d.bits), edgeIn.isResponse(in.d.bits)) + val (e_request, e_response) = (edgeIn.isRequest(in.e.bits), edgeIn.isResponse(in.e.bits)) val a_inc = in.a.fire() && a_first && a_request val b_inc = in.b.fire() && b_first && b_request