From ec6bfde9a3d77f540dd38dedeeba1622b6bd3646 Mon Sep 17 00:00:00 2001
From: Howard Mao <zhehao.mao@gmail.com>
Date: Sat, 21 Nov 2015 16:11:22 -0800
Subject: [PATCH] fix WritebackUnit issue in uncore

---
 src/main/scala/Configs.scala    | 24 ++++++++++++------------
 src/main/scala/RocketChip.scala |  4 ++--
 uncore                          |  2 +-
 3 files changed, 15 insertions(+), 15 deletions(-)

diff --git a/src/main/scala/Configs.scala b/src/main/scala/Configs.scala
index 229c2cba..1ec37c6d 100644
--- a/src/main/scala/Configs.scala
+++ b/src/main/scala/Configs.scala
@@ -60,20 +60,20 @@ class DefaultConfig extends Config (
       case NWays => findBy(CacheName)
       case RowBits => findBy(CacheName)
       case NTLBEntries => findBy(CacheName)
-      case SetIdxOffset => findBy(CacheName)
+      case CacheIdBits => findBy(CacheName)
       case "L1I" => {
         case NSets => Knob("L1I_SETS") //64
         case NWays => Knob("L1I_WAYS") //4
         case RowBits => 4*site(CoreInstBits)
         case NTLBEntries => 8
-        case SetIdxOffset => 0
+        case CacheIdBits => 0
       }:PF
       case "L1D" => {
         case NSets => Knob("L1D_SETS") //64
         case NWays => Knob("L1D_WAYS") //4
         case RowBits => 2*site(CoreDataBits)
         case NTLBEntries => 8
-        case SetIdxOffset => 0
+        case CacheIdBits => 0
       }:PF
       case ECCCode => None
       case Replacer => () => new RandomReplacement(site(NWays))
@@ -91,7 +91,7 @@ class DefaultConfig extends Config (
       case NAcquireTransactors => 7
       case L2StoreDataQueueDepth => 1
       case L2DirectoryRepresentation => new NullRepresentation(site(NTiles))
-      case BuildL2CoherenceManager => (p: Parameters) =>
+      case BuildL2CoherenceManager => (id: Int, p: Parameters) =>
         Module(new L2BroadcastHub()(p.alterPartial({
           case InnerTLId => "L1toL2"
           case OuterTLId => "L2toMC" })))
@@ -212,16 +212,17 @@ class WithL2Cache extends Config(
                             site(NWays)
       case NWays => Knob("L2_WAYS")
       case RowBits => site(TLKey(site(TLId))).dataBitsPerBeat
-      case SetIdxOffset => log2Ceil(site(NMemoryChannels) * site(NBanksPerMemoryChannel))
+      case CacheIdBits => log2Ceil(site(NMemoryChannels) * site(NBanksPerMemoryChannel))
     }: PartialFunction[Any,Any] 
     case NAcquireTransactors => 2
     case NSecondaryMisses => 4
     case L2DirectoryRepresentation => new FullRepresentation(site(NTiles))
-    case BuildL2CoherenceManager => (p: Parameters) =>
+    case BuildL2CoherenceManager => (id: Int, p: Parameters) =>
       Module(new L2HellaCacheBank()(p.alterPartial({
-         case CacheName => "L2Bank"
-         case InnerTLId => "L1toL2"
-         case OuterTLId => "L2toMC"})))
+        case CacheId => id
+        case CacheName => "L2Bank"
+        case InnerTLId => "L1toL2"
+        case OuterTLId => "L2toMC"})))
   },
   knobValues = { case "L2_WAYS" => 8; case "L2_CAPACITY_IN_KB" => 2048 }
 )
@@ -365,6 +366,5 @@ class AccumulatorExampleCPPConfig extends Config(new WithAccumulatorExample ++ n
 class AccumulatorExampleVLSIConfig extends Config(new WithAccumulatorExample ++ new DefaultVLSIConfig)
 
 class SmallL2Config extends Config(
-  new With4L2Ways ++
-  new WithL2Capacity128 ++
-  new DefaultL2Config)
+  new With2MemoryChannels ++ new With4BanksPerMemChannel ++
+  new WithL2Capacity256 ++ new DefaultL2Config)
diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala
index 6299c3e5..bb5af14d 100644
--- a/src/main/scala/RocketChip.scala
+++ b/src/main/scala/RocketChip.scala
@@ -24,7 +24,7 @@ case object NOutstandingMemReqsPerChannel extends Field[Int]
 /** Whether to use the slow backup memory port [VLSI] */
 case object UseBackupMemoryPort extends Field[Boolean]
 /** Function for building some kind of coherence manager agent */
-case object BuildL2CoherenceManager extends Field[Parameters => CoherenceAgent]
+case object BuildL2CoherenceManager extends Field[(Int, Parameters) => CoherenceAgent]
 /** Function for building some kind of tile connected to a reset signal */
 case object BuildTiles extends Field[Seq[(Bool, Parameters) => Tile]]
 /** Start address of the "io" region in the memory map */
@@ -210,7 +210,7 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
 
   // Create point(s) of coherence serialization
   val nManagers = nMemChannels * nBanksPerMemChannel
-  val managerEndpoints = List.fill(nManagers) { p(BuildL2CoherenceManager)(p)}
+  val managerEndpoints = List.tabulate(nManagers){id => p(BuildL2CoherenceManager)(id, p)}
   managerEndpoints.foreach { _.incoherent := io.incoherent }
 
   // Wire the tiles and htif to the TileLink client ports of the L1toL2 network,
diff --git a/uncore b/uncore
index a2409255..9c3cb93c 160000
--- a/uncore
+++ b/uncore
@@ -1 +1 @@
-Subproject commit a2409255c361b922aba540578b7c80e9fca33759
+Subproject commit 9c3cb93c07715d8c017138bed83f46ac41b0067b