Add Cross Cover Property Library (#1149)
Add cover points related to memory error to I/D Cache
This commit is contained in:
Jacob Chang
GitHub
@ -654,9 +654,9 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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when (s2_read) { io.cpu.s2_xcpt.ae.ld := true }
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}
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val s2_isSlavePortAccess = s2_req.phys
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if (usingDataScratchpad) {
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require(!usingVM) // therefore, req.phys means this is a slave-port access
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val s2_isSlavePortAccess = s2_req.phys
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when (s2_isSlavePortAccess) {
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assert(!s2_valid || s2_hit_valid)
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io.cpu.s2_xcpt := 0.U.asTypeOf(io.cpu.s2_xcpt)
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@ -720,8 +720,10 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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metaArb.io.in(5).bits.addr := Cat(io.cpu.req.bits.addr >> untagBits, flushCounter(idxBits-1, 0) << blockOffBits)
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metaArb.io.in(5).bits.way_en := ~UInt(0, nWays)
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metaArb.io.in(5).bits.data := metaArb.io.in(4).bits.data
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// Only flush D$ on FENCE.I if some cached executable regions are untracked.
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if (!edge.manager.managers.forall(m => !m.supportsAcquireT || !m.executable || m.regionType >= RegionType.TRACKED)) {
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val supports_flush = !edge.manager.managers.forall(m => !m.supportsAcquireT || !m.executable || m.regionType >= RegionType.TRACKED)
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if (supports_flush) {
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when (tl_out_a.fire() && !s2_uncached) { flushed := false }
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when (flushing) {
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s1_victim_way := flushCounter >> log2Up(nSets)
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@ -757,13 +759,13 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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io.cpu.perf.tlbMiss := io.ptw.req.fire()
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// report errors
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val (data_error, data_error_uncorrectable, data_error_addr) =
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if (usingDataScratchpad) (s2_valid_data_error, s2_data_error_uncorrectable, s2_req.addr) else {
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(tl_out_c.fire() && inWriteback && writeback_data_error,
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writeback_data_uncorrectable,
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tl_out_c.bits.address)
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}
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{
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val (data_error, data_error_uncorrectable, data_error_addr) =
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if (usingDataScratchpad) (s2_valid_data_error, s2_data_error_uncorrectable, s2_req.addr) else {
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(tl_out_c.fire() && inWriteback && writeback_data_error,
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writeback_data_uncorrectable,
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tl_out_c.bits.address)
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}
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val error_addr =
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Mux(metaArb.io.in(1).valid, Cat(metaArb.io.in(1).bits.data.tag, metaArb.io.in(1).bits.addr(untagBits-1, idxLSB)),
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data_error_addr >> idxLSB) << idxLSB
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@ -797,4 +799,44 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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cover(cond, s"DCACHE_$label", "MemorySystem;;" + desc)
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def ccoverNotScratchpad(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
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if (!usingDataScratchpad) ccover(cond, label, desc)
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if (usingDataScratchpad) {
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val data_error_cover = Seq(
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CoverBoolean(!data_error, Seq("no_data_error")),
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CoverBoolean(data_error && !data_error_uncorrectable, Seq("correctable_data_error")),
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CoverBoolean(data_error && data_error_uncorrectable, Seq("uncorrectable_data_error")))
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val request_source = Seq(
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CoverBoolean(s2_isSlavePortAccess, Seq("from_TL")),
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CoverBoolean(!s2_isSlavePortAccess, Seq("from_CPU")))
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cover(new CrossProperty(
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Seq(data_error_cover, request_source),
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Seq(),
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"MemorySystem;;Scratchpad Memory Bit Flip Cross Covers"))
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} else {
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val data_error_cover = Seq(CoverBoolean(s2_valid_data_error, Seq("data_error")))
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val data_error_type = Seq(
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CoverBoolean(!s2_data_error_uncorrectable, Seq("correctable")),
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CoverBoolean(s2_data_error_uncorrectable, Seq("uncorrectable")))
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val data_error_dirty = Seq(
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CoverBoolean(!s2_victim_dirty, Seq("data_clean")),
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CoverBoolean(s2_victim_dirty, Seq("data_dirty")))
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val request_source = if (supports_flush) {
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Seq(
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CoverBoolean(!flushing, Seq("access")),
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CoverBoolean(flushing, Seq("during_flush")))
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} else {
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Seq(CoverBoolean(true.B, Seq("never_flush")))
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}
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val tag_error_cover = Seq(
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CoverBoolean( !metaArb.io.in(1).valid, Seq("no_tag_error")),
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CoverBoolean( metaArb.io.in(1).valid && !s2_meta_error_uncorrectable, Seq("correctable_tag_error")),
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CoverBoolean( metaArb.io.in(1).valid && s2_meta_error_uncorrectable, Seq("uncorrectable_tag_error")))
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cover(new CrossProperty(
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Seq(data_error_cover, data_error_type, data_error_dirty, request_source, tag_error_cover),
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Seq(),
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"MemorySystem;;Cache Memory Bit Flip Cross Covers"))
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}
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}
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@ -241,6 +241,24 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
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}
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}
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val s1_clk_en = s1_valid || s1_slaveValid
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val s2_tag_hit = RegEnable(s1_tag_hit, s1_clk_en)
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val s2_hit_way = OHToUInt(s2_tag_hit)
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val s2_scratchpad_word_addr = Cat(s2_hit_way, Mux(s2_slaveValid, s1s3_slaveAddr, io.s2_vaddr)(untagBits-1, log2Ceil(wordBits/8)), UInt(0, log2Ceil(wordBits/8)))
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val s2_dout = RegEnable(s1_dout, s1_clk_en)
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val s2_way_mux = Mux1H(s2_tag_hit, s2_dout)
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val s2_tag_disparity = RegEnable(s1_tag_disparity, s1_clk_en).asUInt.orR
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val s2_tl_error = RegEnable(s1_tl_error.asUInt.orR, s1_clk_en)
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val s2_data_decoded = dECC.decode(s2_way_mux)
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val s2_disparity = s2_tag_disparity || s2_data_decoded.error
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val s2_full_word_write = Wire(init = false.B)
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val s1_scratchpad_hit = Mux(s1_slaveValid, lineInScratchpad(scratchpadLine(s1s3_slaveAddr)), addrInScratchpad(io.s1_paddr))
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val s2_scratchpad_hit = RegEnable(s1_scratchpad_hit, s1_clk_en)
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val s2_report_uncorrectable_error = s2_scratchpad_hit && s2_data_decoded.uncorrectable && (s2_valid || (s2_slaveValid && !s2_full_word_write))
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val s2_error_addr = scratchpadBase.map(base => Mux(s2_scratchpad_hit, base + s2_scratchpad_word_addr, 0.U)).getOrElse(0.U)
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// output signals
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outer.icacheParams.latency match {
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case 1 =>
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@ -252,18 +270,7 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
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io.resp.valid := s1_valid && s1_hit
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case 2 =>
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val s1_clk_en = s1_valid || s1_slaveValid
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val s2_tag_hit = RegEnable(s1_tag_hit, s1_clk_en)
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val s2_hit_way = OHToUInt(s2_tag_hit)
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val s2_scratchpad_word_addr = Cat(s2_hit_way, Mux(s2_slaveValid, s1s3_slaveAddr, io.s2_vaddr)(untagBits-1, log2Ceil(wordBits/8)), UInt(0, log2Ceil(wordBits/8)))
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val s2_dout = RegEnable(s1_dout, s1_clk_en)
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val s2_way_mux = Mux1H(s2_tag_hit, s2_dout)
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val s2_tag_disparity = RegEnable(s1_tag_disparity, s1_clk_en).asUInt.orR
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val s2_tl_error = RegEnable(s1_tl_error.asUInt.orR, s1_clk_en)
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val s2_data_decoded = dECC.decode(s2_way_mux)
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val s2_disparity = s2_tag_disparity || s2_data_decoded.error
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val s2_full_word_write = Wire(init = false.B)
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// when some sort of memory bit error have occurred
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when (s2_valid && s2_disparity) { invalidate := true }
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io.resp.bits.data := s2_data_decoded.uncorrected
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@ -271,10 +278,6 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
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io.resp.bits.replay := s2_disparity
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io.resp.valid := s2_valid && s2_hit
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val s1_scratchpad_hit = Mux(s1_slaveValid, lineInScratchpad(scratchpadLine(s1s3_slaveAddr)), addrInScratchpad(io.s1_paddr))
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val s2_scratchpad_hit = RegEnable(s1_scratchpad_hit, s1_clk_en)
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val s2_report_uncorrectable_error = s2_scratchpad_hit && s2_data_decoded.uncorrectable && (s2_valid || (s2_slaveValid && !s2_full_word_write))
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val s2_error_addr = scratchpadBase.map(base => Mux(s2_scratchpad_hit, base + s2_scratchpad_word_addr, 0.U)).getOrElse(0.U)
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io.errors.correctable.foreach { c =>
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c.valid := (s2_valid || s2_slaveValid) && s2_disparity && !s2_report_uncorrectable_error
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c.bits := s2_error_addr
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@ -404,4 +407,36 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
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def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
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cover(cond, s"ICACHE_$label", "MemorySystem;;" + desc)
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val mem_active_valid = Seq(CoverBoolean(s2_valid, Seq("mem_active")))
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val data_error = Seq(
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CoverBoolean(!s2_data_decoded.correctable && !s2_data_decoded.uncorrectable, Seq("no_data_error")),
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CoverBoolean(s2_data_decoded.correctable, Seq("correctable_bit_error")),
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CoverBoolean(s2_data_decoded.uncorrectable, Seq("uncorrectable_bit_error")))
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val request_source = Seq(
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CoverBoolean(!s2_slaveValid, Seq("from_CPU")),
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CoverBoolean(s2_slaveValid, Seq("from_TL"))
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)
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val tag_error = Seq(
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CoverBoolean(!s2_tag_disparity, Seq("no_tag_error")),
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CoverBoolean(s2_tag_disparity, Seq("tag_error"))
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)
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val mem_mode = Seq(
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CoverBoolean(s2_scratchpad_hit, Seq("ITIM_mode")),
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CoverBoolean(!s2_scratchpad_hit, Seq("cache_mode"))
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)
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val error_cross_covers = new CrossProperty(
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Seq(mem_active_valid, data_error, tag_error, request_source, mem_mode),
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Seq(
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// tag error cannot occur in ITIM mode
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Seq("tag_error", "ITIM_mode"),
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// tag is only parity check
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Seq("tag_error", "uncorrectable_bit_error"),
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// Can only respond to TL in ITIM mode
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Seq("from_TL", "cache_mode")
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),
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"MemorySystem;;Memory Bit Flip Cross Covers")
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cover(error_cross_covers)
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}
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