tilelink: add DeadlockDevice
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329a5c35d4
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@ -13,17 +13,13 @@ import scala.math.min
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case class ErrorParams(address: Seq[AddressSet], maxTransfer: Int = 4096)
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case object ErrorParams extends Field[ErrorParams]
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/** Adds a /dev/null slave that generates TL error response messages */
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class TLError(params: ErrorParams, beatBytes: Int = 4)(implicit p: Parameters) extends LazyModule
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{
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val address = params.address
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val device = new SimpleDevice("error-device", Seq("sifive,error0"))
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abstract class DevNullDevice(params: ErrorParams, beatBytes: Int = 4)
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(device: SimpleDevice)
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(implicit p: Parameters) extends LazyModule {
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val xfer = TransferSizes(1, params.maxTransfer)
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val node = TLManagerNode(Seq(TLManagerPortParameters(
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Seq(TLManagerParameters(
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address = address,
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address = params.address,
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resources = device.reg("mem"),
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regionType = RegionType.UNCACHED,
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supportsAcquireT = xfer,
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@ -38,7 +34,12 @@ class TLError(params: ErrorParams, beatBytes: Int = 4)(implicit p: Parameters) e
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beatBytes = beatBytes,
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endSinkId = 1, // can receive GrantAck
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minLatency = 1))) // no bypass needed for this device
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}
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/** Adds a /dev/null slave that generates TL error response messages */
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class TLError(params: ErrorParams, beatBytes: Int = 4)(implicit p: Parameters)
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extends DevNullDevice(params, beatBytes)(new SimpleDevice("error-device", Seq("sifive,error0")))
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{
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lazy val module = new LazyModuleImp(this) {
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import TLMessages._
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import TLPermissions._
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@ -88,6 +89,23 @@ class TLError(params: ErrorParams, beatBytes: Int = 4)(implicit p: Parameters) e
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}
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}
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/** Adds a /dev/null slave that does not raise ready for any incoming traffic.
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* !!! WARNING: This device WILL cause your bus to deadlock for as long as you
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* continue to send traffic to it !!!
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*/
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class DeadlockDevice(params: ErrorParams, beatBytes: Int = 4)(implicit p: Parameters)
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extends DevNullDevice(params, beatBytes)(new SimpleDevice("deadlock-device", Seq("sifive,deadlock0")))
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{
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lazy val module = new LazyModuleImp(this) {
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val (in, _) = node.in(0)
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in.a.ready := Bool(false)
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in.b.valid := Bool(false)
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in.c.ready := Bool(false)
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in.d.valid := Bool(false)
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in.e.ready := Bool(false)
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}
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}
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trait HasSystemErrorSlave extends HasSystemBus {
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private val params = p(ErrorParams)
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val error = LazyModule(new TLError(params, sbus.beatBytes))
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