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tilelink: add DeadlockDevice

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This commit is contained in:
Henry Cook
2017-10-11 12:44:23 -07:00
parent 329a5c35d4
commit ec056535dc
1 changed files with 26 additions and 8 deletions
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34
src/main/scala/devices/tilelink/Error.scala
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@@ -13,17 +13,13 @@ import scala.math.min
case class ErrorParams(address: Seq[AddressSet], maxTransfer: Int = 4096) case class ErrorParams(address: Seq[AddressSet], maxTransfer: Int = 4096)
case object ErrorParams extends Field[ErrorParams] case object ErrorParams extends Field[ErrorParams]
/** Adds a /dev/null slave that generates TL error response messages */ abstract class DevNullDevice(params: ErrorParams, beatBytes: Int = 4)
class TLError(params: ErrorParams, beatBytes: Int = 4)(implicit p: Parameters) extends LazyModule (device: SimpleDevice)
{ (implicit p: Parameters) extends LazyModule {
val address = params.address
val device = new SimpleDevice("error-device", Seq("sifive,error0"))
val xfer = TransferSizes(1, params.maxTransfer) val xfer = TransferSizes(1, params.maxTransfer)
val node = TLManagerNode(Seq(TLManagerPortParameters( val node = TLManagerNode(Seq(TLManagerPortParameters(
Seq(TLManagerParameters( Seq(TLManagerParameters(
address = address, address = params.address,
resources = device.reg("mem"), resources = device.reg("mem"),
regionType = RegionType.UNCACHED, regionType = RegionType.UNCACHED,
supportsAcquireT = xfer, supportsAcquireT = xfer,
@@ -38,7 +34,12 @@ class TLError(params: ErrorParams, beatBytes: Int = 4)(implicit p: Parameters) e
beatBytes = beatBytes, beatBytes = beatBytes,
endSinkId = 1, // can receive GrantAck endSinkId = 1, // can receive GrantAck
minLatency = 1))) // no bypass needed for this device minLatency = 1))) // no bypass needed for this device
}
/** Adds a /dev/null slave that generates TL error response messages */
class TLError(params: ErrorParams, beatBytes: Int = 4)(implicit p: Parameters)
extends DevNullDevice(params, beatBytes)(new SimpleDevice("error-device", Seq("sifive,error0")))
{
lazy val module = new LazyModuleImp(this) { lazy val module = new LazyModuleImp(this) {
import TLMessages._ import TLMessages._
import TLPermissions._ import TLPermissions._
@@ -88,6 +89,23 @@ class TLError(params: ErrorParams, beatBytes: Int = 4)(implicit p: Parameters) e
} }
} }
/** Adds a /dev/null slave that does not raise ready for any incoming traffic.
* !!! WARNING: This device WILL cause your bus to deadlock for as long as you
* continue to send traffic to it !!!
*/
class DeadlockDevice(params: ErrorParams, beatBytes: Int = 4)(implicit p: Parameters)
extends DevNullDevice(params, beatBytes)(new SimpleDevice("deadlock-device", Seq("sifive,deadlock0")))
{
lazy val module = new LazyModuleImp(this) {
val (in, _) = node.in(0)
in.a.ready := Bool(false)
in.b.valid := Bool(false)
in.c.ready := Bool(false)
in.d.valid := Bool(false)
in.e.ready := Bool(false)
}
}
trait HasSystemErrorSlave extends HasSystemBus { trait HasSystemErrorSlave extends HasSystemBus {
private val params = p(ErrorParams) private val params = p(ErrorParams)
val error = LazyModule(new TLError(params, sbus.beatBytes)) val error = LazyModule(new TLError(params, sbus.beatBytes))