From ebe95fa8279a7c0041b2536b7a98b4f07cebb12a Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Thu, 16 Jun 2016 15:15:36 -0700 Subject: [PATCH] fix wmask buffer clearing in L2 agents --- uncore/src/main/scala/broadcast.scala | 8 +++----- uncore/src/main/scala/bufferless.scala | 4 ++-- uncore/src/main/scala/cache.scala | 9 ++++----- uncore/src/main/scala/trackers.scala | 19 +++++++++++++------ 4 files changed, 22 insertions(+), 18 deletions(-) diff --git a/uncore/src/main/scala/broadcast.scala b/uncore/src/main/scala/broadcast.scala index 1c51287f..9f996c23 100644 --- a/uncore/src/main/scala/broadcast.scala +++ b/uncore/src/main/scala/broadcast.scala @@ -122,7 +122,7 @@ class BufferedBroadcastVoluntaryReleaseTracker(trackerId: Int)(implicit p: Param coh = outer_coh.onHit(M_XWR), data = data_buffer(vol_ognt_counter.up.idx)) - quiesce() + quiesce() {} } class BufferedBroadcastAcquireTracker(trackerId: Int)(implicit p: Parameters) @@ -189,13 +189,11 @@ class BufferedBroadcastAcquireTracker(trackerId: Int)(implicit p: Parameters) external_pending = pending_orel || ognt_counter.pending || vol_ognt_counter.pending) when(iacq_is_allocating) { - wmask_buffer.foreach { w => w := UInt(0) } // This is the only reg that must be clear in s_idle initializeProbes() } - initDataInner(io.inner.acquire) + initDataInner(io.inner.acquire, iacq_is_allocating || iacq_is_merging) // Wait for everything to quiesce - quiesce() - + quiesce() { clearWmaskBuffer() } } diff --git a/uncore/src/main/scala/bufferless.scala b/uncore/src/main/scala/bufferless.scala index e5ddcb98..2927c928 100644 --- a/uncore/src/main/scala/bufferless.scala +++ b/uncore/src/main/scala/bufferless.scala @@ -78,7 +78,7 @@ class BufferlessBroadcastVoluntaryReleaseTracker(trackerId: Int)(implicit p: Par outerRelease(coh = outer_coh.onHit(M_XWR)) io.outer.grant.ready := state === s_busy && io.inner.grant.ready // bypass data - quiesce() + quiesce() {} } class BufferlessBroadcastAcquireTracker(trackerId: Int)(implicit p: Parameters) @@ -137,5 +137,5 @@ class BufferlessBroadcastAcquireTracker(trackerId: Int)(implicit p: Parameters) when(iacq_is_allocating) { initializeProbes() } // Wait for everything to quiesce - quiesce() + quiesce() {} } diff --git a/uncore/src/main/scala/cache.scala b/uncore/src/main/scala/cache.scala index 55226168..b67f2621 100644 --- a/uncore/src/main/scala/cache.scala +++ b/uncore/src/main/scala/cache.scala @@ -752,7 +752,7 @@ class CacheVoluntaryReleaseTracker(trackerId: Int)(implicit p: Parameters) pending_writes := addPendingBitWhenBeatHasData(io.inner.release) } - quiesce(s_meta_write) + quiesce(s_meta_write) {} // Checks for illegal behavior assert(!(state === s_meta_resp && io.meta.resp.valid && !io.meta.resp.bits.tag_match), @@ -962,7 +962,6 @@ class CacheAcquireTracker(trackerId: Int)(implicit p: Parameters) // Initialize more transaction metadata. Pla when(iacq_is_allocating) { - wmask_buffer.foreach { w => w := UInt(0) } // This is the only reg that must be clear in s_idle amo_result := UInt(0) pending_meta_write := Bool(false) pending_reads := Mux( // Pick out the specific beats of data that need to be read @@ -973,10 +972,10 @@ class CacheAcquireTracker(trackerId: Int)(implicit p: Parameters) pending_resps := UInt(0) } - initDataInner(io.inner.acquire) + initDataInner(io.inner.acquire, iacq_is_allocating || iacq_is_merging) // Wait for everything to quiesce - quiesce(Mux(pending_meta_write, s_meta_write, s_idle)) + quiesce(Mux(pending_meta_write, s_meta_write, s_idle)) { clearWmaskBuffer() } } class L2WritebackReq(implicit p: Parameters) extends L2Metadata()(p) with HasL2Id { @@ -1056,7 +1055,7 @@ class L2WritebackUnit(val trackerId: Int)(implicit p: Parameters) extends XactTr io.wb.resp.valid := state === s_busy && all_pending_done io.wb.resp.bits.id := xact_id - quiesce() + quiesce() {} def full_representation = io.wb.req.bits.coh.inner.full() // State machine updates and transaction handler metadata intialization diff --git a/uncore/src/main/scala/trackers.scala b/uncore/src/main/scala/trackers.scala index d37ab60e..5852b070 100644 --- a/uncore/src/main/scala/trackers.scala +++ b/uncore/src/main/scala/trackers.scala @@ -28,9 +28,12 @@ abstract class XactTracker(implicit p: Parameters) extends CoherenceAgentModule( override val s_idle :: s_meta_read :: s_meta_resp :: s_wb_req :: s_wb_resp :: s_inner_probe :: s_outer_acquire :: s_busy :: s_meta_write :: Nil = Enum(UInt(), 9) val state = Reg(init=s_idle) - def quiesce(next: UInt = s_idle) { + def quiesce(next: UInt = s_idle)(restore: => Unit) { all_pending_done := !scoreboard.foldLeft(Bool(false))(_||_) - when(state === s_busy && all_pending_done) { state := next } + when(state === s_busy && all_pending_done) { + state := next + restore + } } def pinAllReadyValidLow[T <: Data](b: Bundle) { @@ -129,8 +132,8 @@ trait HasDataBuffer extends HasCoherenceAgentParameters { type TLDataBundle = TLBundle with HasTileLinkData with HasTileLinkBeatId - def initDataInner[T <: Acquire](in: DecoupledIO[T]) { - when(in.fire() && in.bits.hasData()) { + def initDataInner[T <: Acquire](in: DecoupledIO[T], alloc: Bool) { + when(in.fire() && in.bits.hasData() && alloc) { data_buffer(in.bits.addr_beat) := in.bits.data } } @@ -156,8 +159,8 @@ trait HasDataBuffer extends HasCoherenceAgentParameters { trait HasByteWriteMaskBuffer extends HasDataBuffer { val wmask_buffer = Reg(init=Vec.fill(innerDataBeats)(UInt(0, width = innerWriteMaskBits))) - override def initDataInner[T <: Acquire](in: DecoupledIO[T]) { - when(in.fire() && in.bits.hasData()) { + override def initDataInner[T <: Acquire](in: DecoupledIO[T], alloc: Bool) { + when(in.fire() && in.bits.hasData() && alloc) { val beat = in.bits.addr_beat val full = FillInterleaved(8, in.bits.wmask()) data_buffer(beat) := (~full & data_buffer(beat)) | (full & in.bits.data) @@ -171,6 +174,10 @@ trait HasByteWriteMaskBuffer extends HasDataBuffer { val wmask = FillInterleaved(8, wmask_buffer(beat)) data_buffer(beat) := ~wmask & old_data | wmask & new_data } + + def clearWmaskBuffer() { + wmask_buffer.foreach { w => w := UInt(0) } + } } trait HasBlockAddressBuffer extends HasCoherenceAgentParameters {