riscv/rocket-chip
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merge Aqcuire and AcquireData. cache line size coupled to tilelink data size

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This commit is contained in:
Henry Cook
2014-03-29 10:59:07 -07:00
parent e90f2484aa
commit ebdc0a2692
3 changed files with 82 additions and 84 deletions
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9
rocket/src/main/scala/tile.scala
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@ -77,9 +77,8 @@ class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Module
memArb.io.out.grant <> io.tilelink.grant
io.tilelink.grant_ack <> memArb.io.out.grant_ack
dcache.io.mem.probe <> io.tilelink.probe
io.tilelink.release.data <> dcache.io.mem.release.data
io.tilelink.release.meta.valid := dcache.io.mem.release.meta.valid
dcache.io.mem.release.meta.ready := io.tilelink.release.meta.ready
io.tilelink.release.meta.bits := dcache.io.mem.release.meta.bits
io.tilelink.release.meta.bits.payload.client_xact_id := Cat(dcache.io.mem.release.meta.bits.payload.client_xact_id, UInt(dcachePortId, log2Up(memPorts))) // Mimic client id extension done by UncachedTileLinkIOArbiter for Acquires from either client)
io.tilelink.release.valid := dcache.io.mem.release.valid
dcache.io.mem.release.ready := io.tilelink.release.ready
io.tilelink.release.bits := dcache.io.mem.release.bits
io.tilelink.release.bits.payload.client_xact_id := Cat(dcache.io.mem.release.bits.payload.client_xact_id, UInt(dcachePortId, log2Up(memPorts))) // Mimic client id extension done by UncachedTileLinkIOArbiter for Acquires from either client)
}