merge Aqcuire and AcquireData. cache line size coupled to tilelink data size
This commit is contained in:
Henry Cook
@ -6,7 +6,7 @@ import Util._
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case class DCacheConfig(sets: Int, ways: Int,
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nmshr: Int, nrpq: Int, nsdq: Int, ntlb: Int,
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states: Int = 2,
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tl: TileLinkConfiguration,
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code: Code = new IdentityCode,
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narrowRead: Boolean = true,
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reqtagbits: Int = -1, databits: Int = -1)
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@ -17,6 +17,7 @@ case class DCacheConfig(sets: Int, ways: Int,
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require(log2Up(OFFSET_BITS) <= ACQUIRE_SUBWORD_ADDR_BITS)
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require(isPow2(sets))
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require(isPow2(ways)) // TODO: relax this
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def states = tl.co.nClientStates
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def lines = sets*ways
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def dm = ways == 1
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def ppnbits = PADDR_BITS - PGIDX_BITS
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@ -30,15 +31,16 @@ case class DCacheConfig(sets: Int, ways: Int,
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def waybits = log2Up(ways)
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def untagbits = offbits + idxbits
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def tagbits = lineaddrbits - idxbits
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def ramoffbits = log2Up(MEM_DATA_BITS/8)
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def ramoffbits = log2Up(tl.dataBits/8)
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def databytes = databits/8
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def wordoffbits = log2Up(databytes)
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def isNarrowRead = narrowRead && databits*ways % MEM_DATA_BITS == 0
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def isNarrowRead = narrowRead && databits*ways % tl.dataBits == 0
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def refillcycles = CACHE_DATA_SIZE_IN_BYTES*8/tl.dataBits
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val statebits = log2Up(states)
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val metabits = statebits + tagbits
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val encdatabits = code.width(databits)
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val encmetabits = code.width(metabits)
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val wordsperrow = MEM_DATA_BITS/databits
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val wordsperrow = tl.dataBits/databits
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val bitsperrow = wordsperrow*encdatabits
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val lrsc_cycles = 32 // ISA requires 16-insn LRSC sequences to succeed
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}
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@ -120,18 +122,19 @@ class DataWriteReq(implicit val conf: DCacheConfig) extends DCacheBundle {
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val data = Bits(width = conf.bitsperrow)
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}
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class InternalProbe(implicit conf: DCacheConfig, tl: TileLinkConfiguration) extends Probe {
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val client_xact_id = Bits(width = tl.clientXactIdBits)
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class InternalProbe(implicit conf: DCacheConfig) extends Probe()(conf.tl) {
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val client_xact_id = Bits(width = conf.tl.clientXactIdBits)
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override def clone = new InternalProbe().asInstanceOf[this.type]
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}
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class WritebackReq(implicit conf: DCacheConfig, tl: TileLinkConfiguration) extends Bundle {
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class WritebackReq(implicit conf: DCacheConfig) extends Bundle {
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val tag = Bits(width = conf.tagbits)
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val idx = Bits(width = conf.idxbits)
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val way_en = Bits(width = conf.ways)
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val client_xact_id = Bits(width = tl.clientXactIdBits)
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val r_type = UInt(width = tl.co.releaseTypeWidth)
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val client_xact_id = Bits(width = conf.tl.clientXactIdBits)
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val master_xact_id = Bits(width = conf.tl.masterXactIdBits)
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val r_type = UInt(width = conf.tl.co.releaseTypeWidth)
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override def clone = new WritebackReq().asInstanceOf[this.type]
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}
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@ -159,8 +162,8 @@ class MetaWriteReq(implicit val conf: DCacheConfig) extends DCacheBundle {
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val data = new MetaData()
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}
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class MSHR(id: Int)(implicit conf: DCacheConfig, tl: TileLinkConfiguration) extends Module {
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implicit val ln = tl.ln
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class MSHR(id: Int)(implicit conf: DCacheConfig) extends Module {
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implicit val (tl, ln) = (conf.tl, conf.tl.ln)
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val io = new Bundle {
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val req_pri_val = Bool(INPUT)
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val req_pri_rdy = Bool(OUTPUT)
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@ -189,7 +192,7 @@ class MSHR(id: Int)(implicit conf: DCacheConfig, tl: TileLinkConfiguration) exte
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val acquire_type = Reg(UInt())
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val release_type = Reg(UInt())
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val line_state = Reg(UInt())
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val refill_count = Reg(UInt(width = log2Up(REFILL_CYCLES)))
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val refill_count = Reg(UInt(width = log2Up(conf.refillcycles))) // TODO: zero-width wire
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val req = Reg(new MSHRReq())
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val req_cmd = io.req_bits.cmd
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@ -198,7 +201,7 @@ class MSHR(id: Int)(implicit conf: DCacheConfig, tl: TileLinkConfiguration) exte
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val sec_rdy = idx_match && (state === s_wb_req || state === s_wb_resp || state === s_meta_clear || (state === s_refill_req || state === s_refill_resp) && !tl.co.needsTransactionOnSecondaryMiss(req_cmd, io.mem_req.bits))
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val reply = io.mem_grant.valid && io.mem_grant.bits.payload.client_xact_id === UInt(id)
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val refill_done = reply && refill_count.andR
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val refill_done = reply && (if(conf.refillcycles > 1) refill_count.andR else Bool(true))
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val wb_done = reply && (state === s_wb_resp)
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val rpq = Module(new Queue(new Replay, conf.nrpq))
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@ -220,7 +223,7 @@ class MSHR(id: Int)(implicit conf: DCacheConfig, tl: TileLinkConfiguration) exte
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when (state === s_refill_resp) {
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when (refill_done) { state := s_meta_write_req }
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when (reply) {
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refill_count := refill_count + UInt(1)
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if(conf.refillcycles > 1) refill_count := refill_count + UInt(1)
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line_state := tl.co.newStateOnGrant(io.mem_grant.bits.payload, io.mem_req.bits)
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}
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}
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@ -270,7 +273,7 @@ class MSHR(id: Int)(implicit conf: DCacheConfig, tl: TileLinkConfiguration) exte
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io.idx_match := (state != s_invalid) && idx_match
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io.mem_resp := req
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io.mem_resp.addr := Cat(req_idx, refill_count) << conf.ramoffbits
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io.mem_resp.addr := (if(conf.refillcycles > 1) Cat(req_idx, refill_count) else req_idx) << conf.ramoffbits
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io.tag := req.addr >> conf.untagbits
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io.req_pri_rdy := state === s_invalid
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io.req_sec_rdy := sec_rdy && rpq.io.enq.ready
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@ -291,6 +294,7 @@ class MSHR(id: Int)(implicit conf: DCacheConfig, tl: TileLinkConfiguration) exte
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io.wb_req.bits.idx := req_idx
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io.wb_req.bits.way_en := req.way_en
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io.wb_req.bits.client_xact_id := Bits(id)
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io.wb_req.bits.master_xact_id := Bits(0) // DNC
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io.wb_req.bits.r_type := tl.co.getReleaseTypeOnVoluntaryWriteback()
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io.mem_req.valid := state === s_refill_req && ackq.io.enq.ready
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@ -314,8 +318,8 @@ class MSHR(id: Int)(implicit conf: DCacheConfig, tl: TileLinkConfiguration) exte
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}
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}
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class MSHRFile(implicit conf: DCacheConfig, tl: TileLinkConfiguration) extends Module {
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implicit val ln = tl.ln
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class MSHRFile(implicit conf: DCacheConfig) extends Module {
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implicit val (tl, ln) = (conf.tl, conf.tl.ln)
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val io = new Bundle {
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val req = Decoupled(new MSHRReq).flip
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val secondary_miss = Bool(OUTPUT)
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@ -416,22 +420,23 @@ class MSHRFile(implicit conf: DCacheConfig, tl: TileLinkConfiguration) extends M
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}
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class WritebackUnit(implicit conf: DCacheConfig, tl: TileLinkConfiguration) extends Module {
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class WritebackUnit(implicit conf: DCacheConfig) extends Module {
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implicit val tl = conf.tl
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val io = new Bundle {
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val req = Decoupled(new WritebackReq()).flip
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val probe = Decoupled(new WritebackReq()).flip
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val meta_read = Decoupled(new MetaReadReq)
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val data_req = Decoupled(new DataReadReq())
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val data_resp = Bits(INPUT, conf.bitsperrow)
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val release = Decoupled(new Release)
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val release_data = Decoupled(new ReleaseData)
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}
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require(conf.refillcycles == 1) // TODO Currently will issue refillcycles distinct releases; need to merge if rowsize < tilelink.dataSize
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val valid = Reg(init=Bool(false))
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val r1_data_req_fired = Reg(init=Bool(false))
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val r2_data_req_fired = Reg(init=Bool(false))
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val cmd_sent = Reg(Bool())
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val cnt = Reg(UInt(width = log2Up(REFILL_CYCLES+1)))
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val cnt = Reg(UInt(width = log2Up(conf.refillcycles+1)))
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val req = Reg(new WritebackReq)
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when (valid) {
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@ -441,26 +446,18 @@ class WritebackUnit(implicit conf: DCacheConfig, tl: TileLinkConfiguration) exte
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r1_data_req_fired := true
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cnt := cnt + 1
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}
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when (r2_data_req_fired && !io.release_data.ready) {
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when (r2_data_req_fired && !io.release.ready) {
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r1_data_req_fired := false
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r2_data_req_fired := false
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cnt := cnt - Mux[UInt](r1_data_req_fired, 2, 1)
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cnt := (if(conf.refillcycles > 1) cnt - Mux[UInt](r1_data_req_fired, 2, 1) else UInt(0))
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}
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when (!r1_data_req_fired && !r2_data_req_fired && cmd_sent && cnt === REFILL_CYCLES) {
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when (io.release.fire()) {
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cmd_sent := true
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}
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when (!r1_data_req_fired && !r2_data_req_fired && cmd_sent && cnt === conf.refillcycles) {
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valid := false
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}
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when (valid && io.release.ready) {
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cmd_sent := true
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}
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}
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when (io.probe.fire()) {
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valid := true
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cmd_sent := true
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cnt := 0
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req := io.probe.bits
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}
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when (io.req.fire()) {
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valid := true
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@ -469,26 +466,27 @@ class WritebackUnit(implicit conf: DCacheConfig, tl: TileLinkConfiguration) exte
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req := io.req.bits
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}
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val fire = valid && cnt < UInt(REFILL_CYCLES)
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io.req.ready := !valid && !io.probe.valid
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io.probe.ready := !valid
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val fire = valid && cnt < UInt(conf.refillcycles)
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io.req.ready := !valid
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io.data_req.valid := fire
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io.data_req.bits.way_en := req.way_en
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io.data_req.bits.addr := Cat(req.idx, cnt(log2Up(REFILL_CYCLES)-1,0)) << conf.ramoffbits
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io.data_req.bits.addr := (if(conf.refillcycles > 1) Cat(req.idx, cnt(log2Up(conf.refillcycles)-1,0))
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else req.idx) << conf.ramoffbits
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io.release.valid := valid && !cmd_sent
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io.release.valid := valid && r2_data_req_fired
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io.release.bits.r_type := req.r_type
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io.release.bits.addr := Cat(req.tag, req.idx).toUInt
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io.release.bits.client_xact_id := req.client_xact_id
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io.release.bits.master_xact_id := UInt(0)
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io.release_data.valid := r2_data_req_fired
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io.release_data.bits.data := io.data_resp
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io.release.bits.master_xact_id := req.master_xact_id
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io.release.bits.data := io.data_resp
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// We reissue the meta read as it sets up the muxing for s2_data_muxed
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io.meta_read.valid := fire
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io.meta_read.bits.addr := io.release.bits.addr << conf.offbits
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}
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class ProbeUnit(implicit conf: DCacheConfig, tl: TileLinkConfiguration) extends Module {
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class ProbeUnit(implicit conf: DCacheConfig) extends Module {
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implicit val tl = conf.tl
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val io = new Bundle {
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val req = Decoupled(new InternalProbe).flip
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val rep = Decoupled(new Release)
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@ -543,7 +541,7 @@ class ProbeUnit(implicit conf: DCacheConfig, tl: TileLinkConfiguration) extends
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}
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io.req.ready := state === s_invalid
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io.rep.valid := state === s_release
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io.rep.valid := state === s_release && !tl.co.needsWriteback(line_state)
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io.rep.bits := Release(tl.co.getReleaseTypeOnProbe(req, Mux(hit, line_state, tl.co.newStateOnFlush)), req.addr, req.client_xact_id, req.master_xact_id)
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io.meta_read.valid := state === s_meta_read
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@ -559,11 +557,13 @@ class ProbeUnit(implicit conf: DCacheConfig, tl: TileLinkConfiguration) extends
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io.wb_req.bits.way_en := way_en
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io.wb_req.bits.idx := req.addr
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io.wb_req.bits.tag := req.addr >> UInt(conf.idxbits)
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io.wb_req.bits.r_type := UInt(0) // DNC
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io.wb_req.bits.client_xact_id := UInt(0) // DNC
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io.wb_req.bits.r_type := tl.co.getReleaseTypeOnProbe(req, Mux(hit, line_state, tl.co.newStateOnFlush))
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io.wb_req.bits.client_xact_id := req.client_xact_id
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io.wb_req.bits.master_xact_id := req.master_xact_id
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}
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class MetaDataArray(implicit conf: DCacheConfig, tl: TileLinkConfiguration) extends Module {
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class MetaDataArray(implicit conf: DCacheConfig) extends Module {
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implicit val tl = conf.tl
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val io = new Bundle {
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val read = Decoupled(new MetaReadReq).flip
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val write = Decoupled(new MetaWriteReq).flip
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@ -612,7 +612,7 @@ class DataArray(implicit conf: DCacheConfig) extends Module {
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val resp = Vec.fill(conf.wordsperrow){Bits(width = conf.bitsperrow)}
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val r_raddr = RegEnable(io.read.bits.addr, io.read.valid)
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for (p <- 0 until resp.size) {
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val array = Mem(Bits(width=conf.bitsperrow), conf.sets*REFILL_CYCLES, seqRead = true)
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val array = Mem(Bits(width=conf.bitsperrow), conf.sets*conf.refillcycles, seqRead = true)
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when (wway_en.orR && io.write.valid && io.write.bits.wmask(p)) {
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val data = Fill(conf.wordsperrow, io.write.bits.data(conf.encdatabits*(p+1)-1,conf.encdatabits*p))
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val mask = FillInterleaved(conf.encdatabits, wway_en)
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@ -631,7 +631,7 @@ class DataArray(implicit conf: DCacheConfig) extends Module {
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} else {
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val wmask = FillInterleaved(conf.encdatabits, io.write.bits.wmask)
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for (w <- 0 until conf.ways) {
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val array = Mem(Bits(width=conf.bitsperrow), conf.sets*REFILL_CYCLES, seqRead = true)
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val array = Mem(Bits(width=conf.bitsperrow), conf.sets*conf.refillcycles, seqRead = true)
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when (io.write.bits.way_en(w) && io.write.valid) {
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array.write(waddr, io.write.bits.data, wmask)
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}
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@ -727,8 +727,8 @@ class HellaCacheIO(implicit conf: DCacheConfig) extends Bundle {
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val ordered = Bool(INPUT)
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}
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class HellaCache(implicit conf: DCacheConfig, tl: TileLinkConfiguration) extends Module {
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implicit val ln = tl.ln
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class HellaCache(implicit conf: DCacheConfig) extends Module {
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implicit val (tl, ln) = (conf.tl, conf.tl.ln)
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val io = new Bundle {
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val cpu = (new HellaCacheIO).flip
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val mem = new TileLinkIO
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@ -930,16 +930,11 @@ class HellaCache(implicit conf: DCacheConfig, tl: TileLinkConfiguration) extends
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mshrs.io.req.bits.old_meta := Mux(s2_tag_match, MetaData(s2_repl_meta.tag, s2_hit_state), s2_repl_meta)
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mshrs.io.req.bits.way_en := Mux(s2_tag_match, s2_tag_match_way, s2_replaced_way_en)
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mshrs.io.req.bits.data := s2_req.data
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when (mshrs.io.req.fire()) { replacer.miss }
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mshrs.io.mem_grant.valid := io.mem.grant.fire()
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mshrs.io.mem_grant.bits := io.mem.grant.bits
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when (mshrs.io.req.fire()) { replacer.miss }
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io.mem.acquire.meta <> FIFOedLogicalNetworkIOWrapper(mshrs.io.mem_req)
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//TODO io.mem.acquire.data should be connected to uncached store data generator
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//io.mem.acquire.data <> FIFOedLogicalNetworkIOWrapper(TODO)
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io.mem.acquire.data.valid := Bool(false)
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io.mem.acquire.data.bits.payload.data := UInt(0)
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io.mem.acquire <> DecoupledLogicalNetworkIOWrapper(mshrs.io.mem_req)
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// replays
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readArb.io.in(1).valid := mshrs.io.replay.valid
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@ -951,14 +946,13 @@ class HellaCache(implicit conf: DCacheConfig, tl: TileLinkConfiguration) extends
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metaWriteArb.io.in(0) <> mshrs.io.meta_write
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// probes
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val releaseArb = Module(new Arbiter(new Release, 2))
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FIFOedLogicalNetworkIOWrapper(releaseArb.io.out) <> io.mem.release.meta
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DecoupledLogicalNetworkIOWrapper(releaseArb.io.out) <> io.mem.release
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val probe = FIFOedLogicalNetworkIOUnwrapper(io.mem.probe)
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val probe = DecoupledLogicalNetworkIOUnwrapper(io.mem.probe)
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prober.io.req.valid := probe.valid && !lrsc_valid
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probe.ready := prober.io.req.ready && !lrsc_valid
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prober.io.req.bits := probe.bits
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prober.io.rep <> releaseArb.io.in(1)
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prober.io.wb_req <> wb.io.probe
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prober.io.way_en := s2_tag_match_way
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prober.io.line_state := s2_hit_state
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prober.io.meta_read <> metaReadArb.io.in(2)
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@ -974,12 +968,14 @@ class HellaCache(implicit conf: DCacheConfig, tl: TileLinkConfiguration) extends
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writeArb.io.in(1).bits.data := io.mem.grant.bits.payload.data
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// writebacks
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wb.io.req <> mshrs.io.wb_req
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val wbArb = Module(new Arbiter(new WritebackReq, 2))
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prober.io.wb_req <> wbArb.io.in(0)
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mshrs.io.wb_req <> wbArb.io.in(1)
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wbArb.io.out <> wb.io.req
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wb.io.meta_read <> metaReadArb.io.in(3)
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wb.io.data_req <> readArb.io.in(2)
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wb.io.data_resp := s2_data_corrected
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releaseArb.io.in(0) <> wb.io.release
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FIFOedLogicalNetworkIOWrapper(wb.io.release_data) <> io.mem.release.data
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// store->load bypassing
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val s4_valid = Reg(next=s3_valid, init=Bool(false))
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Reference in New Issue
Block a user