Merge pull request #587 from ucb-bar/ahb-fix
ahb: rewrote TLToAHB to avoid retracting requests on stall
This commit is contained in:
Wesley W. Terpstra
GitHub
commit
eb953c40f0
@ -219,3 +219,20 @@ object AddressSet
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if (out.size != n) unify(out) else out.toList
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}
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}
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case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
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{
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require (depth >= 0)
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def isDefined = depth > 0
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def latency = if (isDefined && !flow) 1 else 0
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}
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object BufferParams
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{
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implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
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val default = BufferParams(2)
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val none = BufferParams(0)
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val flow = BufferParams(1, true, false)
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val pipe = BufferParams(1, false, true)
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}
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@ -16,7 +16,7 @@ class RRTest1(address: BigInt)(implicit p: Parameters) extends AHBRegisterRouter
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new AHBRegBundle((), _) with RRTest1Bundle)(
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new AHBRegModule((), _, _) with RRTest1Module)
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class AHBFuzzNative()(implicit p: Parameters) extends LazyModule
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class AHBFuzzNative(aFlow: Boolean)(implicit p: Parameters) extends LazyModule
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{
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val fuzz = LazyModule(new TLFuzzer(5000))
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val model = LazyModule(new TLRAMModel("AHBFuzzNative"))
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@ -25,7 +25,7 @@ class AHBFuzzNative()(implicit p: Parameters) extends LazyModule
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val gpio = LazyModule(new RRTest0(0x100))
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model.node := fuzz.node
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xbar.node := TLToAHB()(TLDelayer(0.1)(model.node))
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xbar.node := TLToAHB(aFlow)(TLDelayer(0.1)(model.node))
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ram.node := xbar.node
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gpio.node := xbar.node
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@ -34,12 +34,12 @@ class AHBFuzzNative()(implicit p: Parameters) extends LazyModule
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}
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}
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class AHBNativeTest()(implicit p: Parameters) extends UnitTest(500000) {
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val dut = Module(LazyModule(new AHBFuzzNative).module)
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class AHBNativeTest(aFlow: Boolean)(implicit p: Parameters) extends UnitTest(500000) {
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val dut = Module(LazyModule(new AHBFuzzNative(aFlow)).module)
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io.finished := dut.io.finished
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}
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class AHBFuzzMaster()(implicit p: Parameters) extends LazyModule
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class AHBFuzzMaster(aFlow: Boolean)(implicit p: Parameters) extends LazyModule
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{
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val node = AHBOutputNode()
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val fuzz = LazyModule(new TLFuzzer(5000))
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@ -47,9 +47,9 @@ class AHBFuzzMaster()(implicit p: Parameters) extends LazyModule
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model.node := fuzz.node
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node :=
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TLToAHB()(
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TLToAHB(aFlow)(
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TLDelayer(0.2)(
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TLBuffer(TLBufferParams.flow)(
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TLBuffer(BufferParams.flow)(
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TLDelayer(0.2)(
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model.node))))
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@ -71,7 +71,7 @@ class AHBFuzzSlave()(implicit p: Parameters) extends LazyModule
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ram.node :=
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TLFragmenter(4, 16)(
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TLDelayer(0.2)(
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TLBuffer(TLBufferParams.flow)(
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TLBuffer(BufferParams.flow)(
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TLDelayer(0.2)(
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AHBToTL()(
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node)))))
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@ -83,9 +83,9 @@ class AHBFuzzSlave()(implicit p: Parameters) extends LazyModule
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}
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}
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class AHBFuzzBridge()(implicit p: Parameters) extends LazyModule
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class AHBFuzzBridge(aFlow: Boolean)(implicit p: Parameters) extends LazyModule
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{
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val master = LazyModule(new AHBFuzzMaster)
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val master = LazyModule(new AHBFuzzMaster(aFlow))
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val slave = LazyModule(new AHBFuzzSlave)
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slave.node := master.node
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@ -95,7 +95,7 @@ class AHBFuzzBridge()(implicit p: Parameters) extends LazyModule
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}
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}
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class AHBBridgeTest()(implicit p: Parameters) extends UnitTest(500000) {
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val dut = Module(LazyModule(new AHBFuzzBridge).module)
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class AHBBridgeTest(aFlow: Boolean)(implicit p: Parameters) extends UnitTest(500000) {
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val dut = Module(LazyModule(new AHBFuzzBridge(aFlow)).module)
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io.finished := dut.io.finished
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}
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@ -56,7 +56,7 @@ class AHBToTL()(implicit p: Parameters) extends LazyModule
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val d_addr = Reg(in.haddr)
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val d_size = Reg(in.hsize)
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when (out.d.valid) { d_recv := Bool(false); d_error := d_error || out.d.bits.error }
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when (out.d.valid) { d_recv := Bool(false) }
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when (out.a.ready) { d_send := Bool(false) }
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val a_count = RegInit(UInt(0, width = 4))
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@ -87,14 +87,12 @@ class AHBToTL()(implicit p: Parameters) extends LazyModule
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when (a_accept) {
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a_count := a_count - UInt(1)
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d_error := d_error || !a_legal
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when ( in.hwrite) { d_send := Bool(true) }
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when (!in.hwrite) { d_recv := Bool(true) }
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when (a_first) {
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a_count := Mux(a_burst_ok, a_burst_mask >> log2Ceil(beatBytes), UInt(0))
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d_send := a_legal
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d_recv := a_legal
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d_error := !a_legal
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d_pause := Bool(false)
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d_write := in.hwrite
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d_addr := in.haddr
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@ -111,7 +109,11 @@ class AHBToTL()(implicit p: Parameters) extends LazyModule
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out.a.bits.data := in.hwdata
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out.a.bits.mask := maskGen(d_addr, d_size, beatBytes)
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// Save the error for the last beat (so the master can't cancel the burst)
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d_error :=
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(d_error && !(a_first && in.hready)) || // clear error when a new beat starts
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(a_accept && !a_legal) || // error if the address requested is illegal
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(out.d.valid && out.d.bits.error) // error if TL reports an error
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// When we report an error, we need to be hreadyout LOW for one cycle
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val inject_error = d_last && (d_error || (out.d.valid && out.d.bits.error))
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when (inject_error) { d_pause := Bool(true) }
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@ -16,7 +16,7 @@ class RRTest1(address: BigInt)(implicit p: Parameters) extends APBRegisterRouter
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new APBRegBundle((), _) with RRTest1Bundle)(
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new APBRegModule((), _, _) with RRTest1Module)
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class APBFuzzBridge()(implicit p: Parameters) extends LazyModule
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class APBFuzzBridge(aFlow: Boolean)(implicit p: Parameters) extends LazyModule
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{
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val fuzz = LazyModule(new TLFuzzer(5000))
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val model = LazyModule(new TLRAMModel("APBFuzzMaster"))
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@ -28,9 +28,9 @@ class APBFuzzBridge()(implicit p: Parameters) extends LazyModule
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ram.node := xbar.node
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gpio.node := xbar.node
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xbar.node :=
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TLToAPB()(
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TLToAPB(aFlow)(
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TLDelayer(0.2)(
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TLBuffer(TLBufferParams.flow)(
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TLBuffer(BufferParams.flow)(
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TLDelayer(0.2)(
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model.node))))
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@ -39,7 +39,7 @@ class APBFuzzBridge()(implicit p: Parameters) extends LazyModule
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}
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}
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class APBBridgeTest()(implicit p: Parameters) extends UnitTest(500000) {
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val dut = Module(LazyModule(new APBFuzzBridge).module)
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class APBBridgeTest(aFlow: Boolean)(implicit p: Parameters) extends UnitTest(500000) {
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val dut = Module(LazyModule(new APBFuzzBridge(aFlow)).module)
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io.finished := dut.io.finished
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}
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@ -4,22 +4,26 @@ package uncore.axi4
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import Chisel._
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import chisel3.internal.sourceinfo.SourceInfo
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import chisel3.util.IrrevocableIO
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import config._
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import diplomacy._
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import scala.math.{min,max}
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// pipe is only used if a queue has depth = 1
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class AXI4Buffer(aw: Int = 2, w: Int = 2, b: Int = 2, ar: Int = 2, r: Int = 2, pipe: Boolean = true)(implicit p: Parameters) extends LazyModule
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class AXI4Buffer(
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aw: BufferParams,
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w: BufferParams,
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b: BufferParams,
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ar: BufferParams,
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r: BufferParams)(implicit p: Parameters) extends LazyModule
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{
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require (aw >= 0)
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require (w >= 0)
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require (b >= 0)
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require (ar >= 0)
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require (r >= 0)
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def this(aw: BufferParams, br: BufferParams)(implicit p: Parameters) = this(aw, aw, br, aw, br)
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def this(x: BufferParams)(implicit p: Parameters) = this(x, x)
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def this()(implicit p: Parameters) = this(BufferParams.default)
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val node = AXI4AdapterNode(
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masterFn = { p => p },
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slaveFn = { p => p.copy(minLatency = p.minLatency + min(1,min(aw,ar)) + min(1,min(r,b))) })
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slaveFn = { p => p.copy(minLatency = p.minLatency + min(aw.latency,ar.latency) + min(r.latency,b.latency)) })
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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@ -27,12 +31,20 @@ class AXI4Buffer(aw: Int = 2, w: Int = 2, b: Int = 2, ar: Int = 2, r: Int = 2, p
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val out = node.bundleOut
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}
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def buffer[T <: Data](config: BufferParams, data: IrrevocableIO[T]): IrrevocableIO[T] = {
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if (config.isDefined) {
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Queue.irrevocable(data, config.depth, pipe=config.pipe, flow=config.flow)
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} else {
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data
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}
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}
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((io.in zip io.out) zip (node.edgesIn zip node.edgesOut)) foreach { case ((in, out), (edgeIn, edgeOut)) =>
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if (aw>0) { out.aw <> Queue(in .aw, aw, pipe && aw<2) } else { out.aw <> in .aw }
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if (w >0) { out.w <> Queue(in .w, w, pipe && w <2) } else { out.w <> in .w }
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if (b >0) { in .b <> Queue(out.b, b, pipe && b <2) } else { in .b <> out.b }
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if (ar>0) { out.ar <> Queue(in .ar, ar, pipe && ar<2) } else { out.ar <> in .ar }
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if (r >0) { in .r <> Queue(out.r, r, pipe && r <2) } else { in .r <> out.r }
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out.aw <> buffer(aw, in .aw)
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out.w <> buffer(w, in .w)
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in .b <> buffer(b, out.b)
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out.ar <> buffer(ar, in .ar)
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in .r <> buffer(r, out.r)
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}
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}
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}
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@ -40,13 +52,16 @@ class AXI4Buffer(aw: Int = 2, w: Int = 2, b: Int = 2, ar: Int = 2, r: Int = 2, p
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object AXI4Buffer
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{
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// applied to the AXI4 source node; y.node := AXI4Buffer(x.node)
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def apply() (x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = apply(2)(x)
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def apply(entries: Int) (x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = apply(entries, true)(x)
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def apply(entries: Int, pipe: Boolean) (x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = apply(entries, entries, pipe)(x)
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def apply(aw: Int, br: Int) (x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = apply(aw, br, true)(x)
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def apply(aw: Int, br: Int, pipe: Boolean)(x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = apply(aw, aw, br, aw, br, pipe)(x)
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def apply(aw: Int, w: Int, b: Int, ar: Int, r: Int, pipe: Boolean = true)(x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = {
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val buffer = LazyModule(new AXI4Buffer(aw, w, b, ar, r, pipe))
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def apply() (x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = apply(BufferParams.default)(x)
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def apply(z: BufferParams) (x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = apply(z, z)(x)
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def apply(aw: BufferParams, br: BufferParams)(x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = apply(aw, aw, br, aw, br)(x)
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def apply(
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aw: BufferParams,
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w: BufferParams,
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b: BufferParams,
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ar: BufferParams,
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r: BufferParams)(x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = {
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val buffer = LazyModule(new AXI4Buffer(aw, w, b, ar, r))
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buffer.node := x
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buffer.node
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}
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@ -25,7 +25,7 @@ class AXI4LiteFuzzRAM()(implicit p: Parameters) extends LazyModule
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val ram = LazyModule(new AXI4RAM(AddressSet(0x0, 0x3ff)))
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model.node := fuzz.node
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xbar.node := TLDelayer(0.1)(TLBuffer(TLBufferParams.flow)(TLDelayer(0.2)(model.node)))
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xbar.node := TLDelayer(0.1)(TLBuffer(BufferParams.flow)(TLDelayer(0.2)(model.node)))
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ram.node := AXI4Fragmenter(lite=true)(TLToAXI4(0, true )(xbar.node))
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gpio.node := AXI4Fragmenter(lite=true)(TLToAXI4(0, false)(xbar.node))
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@ -48,7 +48,7 @@ class AXI4FullFuzzRAM()(implicit p: Parameters) extends LazyModule
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val ram = LazyModule(new AXI4RAM(AddressSet(0x0, 0x3ff)))
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model.node := fuzz.node
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xbar.node := TLDelayer(0.1)(TLBuffer(TLBufferParams.flow)(TLDelayer(0.2)(model.node)))
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xbar.node := TLDelayer(0.1)(TLBuffer(BufferParams.flow)(TLDelayer(0.2)(model.node)))
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ram.node := AXI4Fragmenter(lite=false, maxInFlight = 2)(TLToAXI4(4,false)(xbar.node))
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gpio.node := AXI4Fragmenter(lite=false, maxInFlight = 5)(TLToAXI4(4,true )(xbar.node))
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@ -72,7 +72,7 @@ class AXI4FuzzMaster()(implicit p: Parameters) extends LazyModule
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node :=
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TLToAXI4(4)(
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TLDelayer(0.1)(
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TLBuffer(TLBufferParams.flow)(
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TLBuffer(BufferParams.flow)(
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TLDelayer(0.1)(
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model.node))))
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@ -94,7 +94,7 @@ class AXI4FuzzSlave()(implicit p: Parameters) extends LazyModule
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ram.node :=
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TLFragmenter(4, 16)(
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TLDelayer(0.1)(
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TLBuffer(TLBufferParams.flow)(
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TLBuffer(BufferParams.flow)(
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TLDelayer(0.1)(
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AXI4ToTL()(
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AXI4Fragmenter()(
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@ -8,33 +8,16 @@ import config._
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import diplomacy._
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import scala.math.{min,max}
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case class TLBufferParams(depth: Int, flow: Boolean, pipe: Boolean)
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{
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require (depth >= 0)
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def isDefined = depth > 0
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def latency = if (isDefined && !flow) 1 else 0
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}
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object TLBufferParams
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{
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implicit def apply(depth: Int): TLBufferParams = TLBufferParams(depth, false, false)
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val default = TLBufferParams(2)
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val none = TLBufferParams(0)
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val flow = TLBufferParams(1, true, false)
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val pipe = TLBufferParams(1, false, true)
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}
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class TLBuffer(
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a: TLBufferParams,
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b: TLBufferParams,
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c: TLBufferParams,
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d: TLBufferParams,
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e: TLBufferParams)(implicit p: Parameters) extends LazyModule
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a: BufferParams,
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b: BufferParams,
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c: BufferParams,
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d: BufferParams,
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e: BufferParams)(implicit p: Parameters) extends LazyModule
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{
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def this(ace: TLBufferParams, bd: TLBufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace)
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def this(abcde: TLBufferParams)(implicit p: Parameters) = this(abcde, abcde)
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def this()(implicit p: Parameters) = this(TLBufferParams.default)
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def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace)
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def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde)
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def this()(implicit p: Parameters) = this(BufferParams.default)
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val node = TLAdapterNode(
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clientFn = { p => p.copy(minLatency = p.minLatency + b.latency + c.latency) },
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@ -46,7 +29,7 @@ class TLBuffer(
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val out = node.bundleOut
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}
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def buffer[T <: Data](config: TLBufferParams, data: DecoupledIO[T]): DecoupledIO[T] = {
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def buffer[T <: Data](config: BufferParams, data: DecoupledIO[T]): DecoupledIO[T] = {
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if (config.isDefined) {
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Queue(data, config.depth, pipe=config.pipe, flow=config.flow)
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} else {
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@ -77,15 +60,15 @@ class TLBuffer(
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object TLBuffer
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{
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// applied to the TL source node; y.node := TLBuffer(x.node)
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def apply() (x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = apply(TLBufferParams.default)(x)
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def apply(abcde: TLBufferParams) (x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = apply(abcde, abcde)(x)
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def apply(ace: TLBufferParams, bd: TLBufferParams)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = apply(ace, bd, ace, bd, ace)(x)
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def apply() (x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = apply(BufferParams.default)(x)
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def apply(abcde: BufferParams) (x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = apply(abcde, abcde)(x)
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def apply(ace: BufferParams, bd: BufferParams)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = apply(ace, bd, ace, bd, ace)(x)
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def apply(
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a: TLBufferParams,
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b: TLBufferParams,
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c: TLBufferParams,
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d: TLBufferParams,
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e: TLBufferParams)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
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a: BufferParams,
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b: BufferParams,
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c: BufferParams,
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d: BufferParams,
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e: BufferParams)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
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val buffer = LazyModule(new TLBuffer(a, b, c, d, e))
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buffer.node := x
|
||||
buffer.node
|
||||
|
||||
@ -25,12 +25,29 @@ case class TLToAHBNode() extends MixedAdapterNode(TLImp, AHBImp)(
|
||||
nodePath = s.nodePath,
|
||||
supportsGet = s.supportsRead,
|
||||
supportsPutFull = s.supportsWrite, // but not PutPartial
|
||||
fifoId = Some(0)) // a common FIFO domain
|
||||
fifoId = Some(0))
|
||||
}
|
||||
TLManagerPortParameters(managers, beatBytes, 1, 1)
|
||||
})
|
||||
|
||||
class TLToAHB(val combinational: Boolean = true)(implicit p: Parameters) extends LazyModule
|
||||
class AHBControlBundle(params: TLEdge) extends util.GenericParameterizedBundle(params)
|
||||
{
|
||||
val full = Bool()
|
||||
val send = Bool() // => full+data
|
||||
val first = Bool()
|
||||
val last = Bool()
|
||||
val write = Bool()
|
||||
val size = UInt(width = params.bundle.sizeBits)
|
||||
val source = UInt(width = params.bundle.sourceBits)
|
||||
val hsize = UInt(width = AHBParameters.sizeBits)
|
||||
val hburst = UInt(width = AHBParameters.burstBits)
|
||||
val addr = UInt(width = params.bundle.addressBits)
|
||||
val data = UInt(width = params.bundle.dataBits)
|
||||
}
|
||||
|
||||
// The input side has either a flow queue (aFlow=true) or a pipe queue (aFlow=false)
|
||||
// The output side always has a flow queue
|
||||
class TLToAHB(val aFlow: Boolean = false)(implicit p: Parameters) extends LazyModule
|
||||
{
|
||||
val node = TLToAHBNode()
|
||||
|
||||
@ -46,82 +63,129 @@ class TLToAHB(val combinational: Boolean = true)(implicit p: Parameters) extends
|
||||
val lgMax = log2Ceil(maxTransfer)
|
||||
val lgBytes = log2Ceil(beatBytes)
|
||||
|
||||
// AHB has no cache coherence
|
||||
in.b.valid := Bool(false)
|
||||
in.c.ready := Bool(true)
|
||||
in.e.ready := Bool(true)
|
||||
// Initial FSM state
|
||||
val resetState = Wire(new AHBControlBundle(edgeIn))
|
||||
resetState.full := Bool(false)
|
||||
resetState.send := Bool(false)
|
||||
resetState.first := Bool(true)
|
||||
// These are needed to appease AHB VIP:
|
||||
resetState.hsize := UInt(0)
|
||||
resetState.hburst:= UInt(0)
|
||||
resetState.addr := UInt(0)
|
||||
|
||||
// The stages of the combinational pipeline
|
||||
val reg = RegInit(resetState)
|
||||
val send = Wire(init = reg)
|
||||
val step = Wire(init = send)
|
||||
val next = Wire(init = step)
|
||||
reg := next
|
||||
|
||||
// Advance the FSM based on the result of this AHB beat
|
||||
when (send.send && !out.hreadyout) /* retry AHB */ {
|
||||
step.full := Bool(true)
|
||||
step.send := Bool(true)
|
||||
} .elsewhen (send.full && !send.send) /* retry beat */ {
|
||||
step.full := Bool(true)
|
||||
step.send := Bool(false)
|
||||
} .elsewhen (send.full && !send.last) /* continue burst */ {
|
||||
step.full := Bool(true)
|
||||
step.send := Bool(false) // => looks like a retry to injector
|
||||
step.first := Bool(false)
|
||||
step.last := (if (lgBytes + 1 >= lgMax) Bool(true) else
|
||||
!((UIntToOH1(send.size, lgMax) & ~send.addr) >> (lgBytes + 1)).orR())
|
||||
step.addr := Cat(send.addr(edgeIn.bundle.addressBits-1, lgMax), send.addr(lgMax-1, 0) + UInt(beatBytes))
|
||||
} .otherwise /* new burst */ {
|
||||
step.full := Bool(false)
|
||||
step.send := Bool(false)
|
||||
step.first := Bool(true)
|
||||
}
|
||||
|
||||
val d_block = Wire(Bool())
|
||||
val pre = if (aFlow) reg else step
|
||||
val post = if (aFlow) send else next
|
||||
|
||||
// Transform TL size into AHB hsize+hburst
|
||||
val a_sizeDelta = Cat(UInt(0, width = 1), in.a.bits.size) - UInt(lgBytes+1)
|
||||
val a_singleBeat = Bool(lgBytes >= lgMax) || a_sizeDelta(edgeIn.bundle.sizeBits)
|
||||
val a_logBeats1 = a_sizeDelta(edgeIn.bundle.sizeBits-1, 0)
|
||||
|
||||
// Pulse this every time we commit to sending an AHB request
|
||||
val a_commit = Wire(Bool())
|
||||
|
||||
// Inject A channel into FSM
|
||||
when (pre.send) /* busy */ {
|
||||
a_commit := Bool(false)
|
||||
in.a.ready := Bool(false)
|
||||
} .elsewhen (pre.full) /* retry beat (or continue burst) */ {
|
||||
post.send := !d_block && (!pre.write || in.a.valid)
|
||||
post.data := in.a.bits.data
|
||||
a_commit := !d_block && !pre.write // only read beats commit to a D beat answer
|
||||
in.a.ready := !d_block && pre.write
|
||||
} .otherwise /* new burst */ {
|
||||
a_commit := in.a.fire() // every first beat commits to a D beat answer
|
||||
in.a.ready := !d_block
|
||||
when (in.a.fire()) {
|
||||
post.full := Bool(true)
|
||||
post.send := Bool(true)
|
||||
post.last := a_singleBeat
|
||||
post.write := edgeIn.hasData(in.a.bits)
|
||||
post.size := in.a.bits.size
|
||||
post.source:= in.a.bits.source
|
||||
post.hsize := Mux(a_singleBeat, in.a.bits.size, UInt(lgBytes))
|
||||
post.hburst:= Mux(a_singleBeat, BURST_SINGLE, (a_logBeats1<<1) | UInt(1))
|
||||
post.addr := in.a.bits.address
|
||||
post.data := in.a.bits.data
|
||||
}
|
||||
}
|
||||
|
||||
out.hmastlock := Bool(false) // for now
|
||||
out.htrans := Mux(send.send, Mux(send.first, TRANS_NONSEQ, TRANS_SEQ), Mux(send.first, TRANS_IDLE, TRANS_BUSY))
|
||||
out.hsel := send.send || !send.first
|
||||
out.hready := out.hreadyout
|
||||
out.hwrite := send.write
|
||||
out.haddr := send.addr
|
||||
out.hsize := send.hsize
|
||||
out.hburst := send.hburst
|
||||
out.hprot := PROT_DEFAULT
|
||||
out.hwdata := RegEnable(send.data, out.hreadyout)
|
||||
|
||||
// We need a skidpad to capture D output:
|
||||
// We cannot know if the D response will be accepted until we have
|
||||
// presented it on D as valid. We also can't back-pressure AHB in the
|
||||
// data phase. Therefore, we must have enough space to save the data
|
||||
// phase result. Whenever we have a queued response, we can not allow
|
||||
// AHB to present new responses, so we must quash the address phase.
|
||||
// data phase. Therefore, we must have enough space to save the all
|
||||
// commited AHB requests (A+D phases = 2). To decouple d_ready from
|
||||
// a_ready and htrans, we add another entry for aFlow=false.
|
||||
val depth = if (aFlow) 2 else 3
|
||||
val d = Wire(in.d)
|
||||
in.d <> Queue(d, 1, flow = true)
|
||||
val a_quash = in.d.valid && !in.d.ready
|
||||
in.d <> Queue(d, depth, flow=true)
|
||||
assert (!d.valid || d.ready)
|
||||
|
||||
val d_flight = RegInit(UInt(0, width = 2))
|
||||
assert (d_flight <= UInt(depth))
|
||||
d_flight := d_flight + a_commit.asUInt - in.d.fire().asUInt
|
||||
d_block := d_flight >= UInt(depth)
|
||||
|
||||
// Record what is coming out in d_phase
|
||||
val d_valid = RegInit(Bool(false))
|
||||
val d_hasData = Reg(Bool())
|
||||
val d_error = Reg(Bool())
|
||||
val d_addr_lo = Reg(UInt(width = lgBytes))
|
||||
val d_source = Reg(UInt())
|
||||
val d_size = Reg(UInt())
|
||||
val d_write = RegEnable(send.write, out.hreadyout)
|
||||
val d_source = RegEnable(send.source, out.hreadyout)
|
||||
val d_addr = RegEnable(send.addr, out.hreadyout)
|
||||
val d_size = RegEnable(send.size, out.hreadyout)
|
||||
|
||||
when (out.hreadyout) { d_error := d_error || out.hresp }
|
||||
when (d.fire()) { d_valid := Bool(false) }
|
||||
when (out.hreadyout) {
|
||||
d_valid := send.send && (send.last || !send.write)
|
||||
when (out.hresp) { d_error := d_write }
|
||||
when (send.first) { d_error := Bool(false) }
|
||||
}
|
||||
|
||||
d.valid := d_valid && out.hreadyout
|
||||
d.bits := edgeIn.AccessAck(d_addr_lo, UInt(0), d_source, d_size, out.hrdata, out.hresp || d_error)
|
||||
d.bits.opcode := Mux(d_hasData, TLMessages.AccessAckData, TLMessages.AccessAck)
|
||||
d.bits := edgeIn.AccessAck(d_addr, UInt(0), d_source, d_size, out.hrdata, out.hresp || d_error)
|
||||
d.bits.opcode := Mux(d_write, TLMessages.AccessAck, TLMessages.AccessAckData)
|
||||
|
||||
// We need an irrevocable input for AHB to stall on read bursts
|
||||
// We also need the values to NOT change when valid goes low => 1 entry only
|
||||
val a = Queue(in.a, 1, flow = combinational, pipe = !combinational)
|
||||
val a_valid = a.valid && !a_quash
|
||||
|
||||
// This is lot like TLEdge.firstlast, but counts beats also for single-beat TL types
|
||||
val a_size = edgeIn.size(a.bits)
|
||||
val a_beats1 = UIntToOH1(a_size, lgMax) >> lgBytes
|
||||
val a_counter = RegInit(UInt(0, width = log2Up(maxTransfer/beatBytes)))
|
||||
val a_counter1 = a_counter - UInt(1)
|
||||
val a_first = a_counter === UInt(0)
|
||||
val a_last = a_counter === UInt(1) || a_beats1 === UInt(0)
|
||||
val a_offset = (a_beats1 & ~a_counter1) << lgBytes
|
||||
val a_hasData = edgeIn.hasData(a.bits)
|
||||
|
||||
// Expand no-data A-channel requests into multiple beats
|
||||
a.ready := (a_hasData || a_last) && out.hreadyout && !a_quash
|
||||
when (a_valid && out.hreadyout) {
|
||||
a_counter := Mux(a_first, a_beats1, a_counter1)
|
||||
d_valid := !a_hasData || a_last
|
||||
// Record what will be in the data phase
|
||||
when (a_first) {
|
||||
d_hasData := !a_hasData
|
||||
d_error := Bool(false)
|
||||
d_addr_lo := a.bits.address
|
||||
d_source := a.bits.source
|
||||
d_size := a.bits.size
|
||||
}
|
||||
}
|
||||
|
||||
// Transform TL size into AHB hsize+hburst
|
||||
val a_size_bits = a_size.getWidth
|
||||
val a_sizeDelta = Cat(UInt(0, width = 1), a_size) - UInt(lgBytes+1)
|
||||
val a_singleBeat = a_sizeDelta(a_size_bits)
|
||||
val a_logBeats1 = a_sizeDelta(a_size_bits-1, 0)
|
||||
|
||||
out.hmastlock := Bool(false) // for now
|
||||
out.htrans := Mux(a_valid, Mux(a_first, TRANS_NONSEQ, TRANS_SEQ), Mux(a_first, TRANS_IDLE, TRANS_BUSY))
|
||||
out.hsel := a_valid || !a_first
|
||||
out.hready := out.hreadyout
|
||||
out.hwrite := a_hasData
|
||||
out.haddr := a.bits.address | a_offset
|
||||
out.hsize := Mux(a_singleBeat, a.bits.size, UInt(lgBytes))
|
||||
out.hburst := Mux(a_singleBeat, BURST_SINGLE, (a_logBeats1<<1) | UInt(1))
|
||||
out.hprot := PROT_DEFAULT
|
||||
out.hwdata := RegEnable(a.bits.data, a.fire())
|
||||
// AHB has no cache coherence
|
||||
in.b.valid := Bool(false)
|
||||
in.c.ready := Bool(true)
|
||||
in.e.ready := Bool(true)
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -129,8 +193,8 @@ class TLToAHB(val combinational: Boolean = true)(implicit p: Parameters) extends
|
||||
object TLToAHB
|
||||
{
|
||||
// applied to the TL source node; y.node := TLToAHB()(x.node)
|
||||
def apply(combinational: Boolean = true)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AHBOutwardNode = {
|
||||
val ahb = LazyModule(new TLToAHB(combinational))
|
||||
def apply(aFlow: Boolean = true)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AHBOutwardNode = {
|
||||
val ahb = LazyModule(new TLToAHB(aFlow))
|
||||
ahb.node := x
|
||||
ahb.node
|
||||
}
|
||||
|
||||
@ -31,7 +31,9 @@ case class TLToAPBNode() extends MixedAdapterNode(TLImp, APBImp)(
|
||||
TLManagerPortParameters(managers, beatBytes, 1, 0)
|
||||
})
|
||||
|
||||
class TLToAPB(combinational: Boolean = true)(implicit p: Parameters) extends LazyModule
|
||||
// The input side has either a flow queue (aFlow=true) or a pipe queue (aFlow=false)
|
||||
// The output side always has a flow queue
|
||||
class TLToAPB(val aFlow: Boolean = true)(implicit p: Parameters) extends LazyModule
|
||||
{
|
||||
val node = TLToAPBNode()
|
||||
|
||||
@ -60,7 +62,7 @@ class TLToAPB(combinational: Boolean = true)(implicit p: Parameters) extends Laz
|
||||
in.d <> Queue(d, 1, flow = true)
|
||||
|
||||
// We need an irrevocable input for APB to stall
|
||||
val a = Queue(in.a, 1, flow = combinational, pipe = !combinational)
|
||||
val a = Queue(in.a, 1, flow = aFlow, pipe = !aFlow)
|
||||
|
||||
val a_enable = RegInit(Bool(false))
|
||||
val a_sel = a.valid && RegNext(!in.d.valid || in.d.ready)
|
||||
@ -90,8 +92,8 @@ class TLToAPB(combinational: Boolean = true)(implicit p: Parameters) extends Laz
|
||||
object TLToAPB
|
||||
{
|
||||
// applied to the TL source node; y.node := TLToAPB()(x.node)
|
||||
def apply(combinational: Boolean = true)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): APBOutwardNode = {
|
||||
val apb = LazyModule(new TLToAPB(combinational))
|
||||
def apply(aFlow: Boolean = true)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): APBOutwardNode = {
|
||||
val apb = LazyModule(new TLToAPB(aFlow))
|
||||
apb.node := x
|
||||
apb.node
|
||||
}
|
||||
|
||||
@ -12,9 +12,11 @@ class WithUncoreUnitTests extends Config((site, here, up) => {
|
||||
implicit val p = q
|
||||
Seq(
|
||||
Module(new uncore.tilelink2.TLFuzzRAMTest),
|
||||
Module(new uncore.ahb.AHBBridgeTest),
|
||||
Module(new uncore.ahb.AHBNativeTest),
|
||||
Module(new uncore.apb.APBBridgeTest),
|
||||
Module(new uncore.ahb.AHBBridgeTest(true)),
|
||||
Module(new uncore.ahb.AHBNativeTest(true)),
|
||||
Module(new uncore.ahb.AHBNativeTest(false)),
|
||||
Module(new uncore.apb.APBBridgeTest(true)),
|
||||
Module(new uncore.apb.APBBridgeTest(false)),
|
||||
Module(new uncore.axi4.AXI4LiteFuzzRAMTest),
|
||||
Module(new uncore.axi4.AXI4FullFuzzRAMTest),
|
||||
Module(new uncore.axi4.AXI4BridgeTest)) }
|
||||
|
||||
Loading…
Reference in New Issue
Block a user