riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

reduce superfluous replays

Browse Source 
we only replay after a cache miss if we mis-scheduled the use of a load.
This commit is contained in:
Andrew Waterman
2012-01-01 21:28:38 -08:00
parent efc623cc36
commit eb657dd250
4 changed files with 32 additions and 19 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
rocket/src/main/scala/consts.scala
View File

@ -68,9 +68,10 @@ object Constants
val WB_X = UFix(0, 3);
val WB_PC = UFix(0, 3);
val WB_ALU = UFix(1, 3);
val WB_PCR = UFix(2, 3);
val WB_TSC = UFix(3, 3);
val WB_PCR = UFix(1, 3);
val WB_ALU = UFix(2, 3);
val WB_TSC = UFix(4, 3);
val WB_IRT = UFix(5, 3);
val N = UFix(0, 1);
val Y = UFix(1, 1);