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new RocketChipBackend implementation

This commit is contained in:
Donggyu Kim 2014-09-23 17:37:54 -07:00 committed by Yunsup Lee
parent f2ca887de3
commit eb384f6461

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@ -23,46 +23,30 @@ class RocketChipBackend extends VerilogBackend
} }
def addMemPin(c: Module) = { def addMemPin(c: Module) = {
for (mod <- Module.components; node <- mod.nodes) { for (m <- Driver.components) {
if (node.isInstanceOf[Mem[ _ ]] && node.component != null && node.asInstanceOf[Mem[_]].seqRead) { m bfs { _ match {
connectMemPin(c, node.component, node) case mem: Mem[_] if mem.seqRead =>
} connectMemPin(m, mem)
case _ =>
} }
} }
} }
def connectMemPin(topC: Module, c: Module, p: Node): Unit = { def connectInitPin(c: Module) {
var isNewPin = false initMap(c) = c.addPin(Bool(INPUT), "init")
val compInitPin = if (!(initMap contains c.parent)) connectInitPin(c.parent)
if (initMap.contains(c)) { initMap(c) := initMap(c.parent)
initMap(c) }
} else {
isNewPin = true
val res = Bool(INPUT)
res.isIo = true
res
}
p.inputs += compInitPin def connectMemPin(c: Module, mem: Mem[_]) {
if (!(initMap contains c)) connectInitPin(c)
if (isNewPin) { mem.inputs += initMap(c)
compInitPin.setName("init")
c.io.asInstanceOf[Bundle] += compInitPin
compInitPin.component = c
initMap += (c -> compInitPin)
connectMemPin(topC, c.parent, compInitPin)
}
} }
def addTopLevelPin(c: Module) = { def addTopLevelPin(c: Module) = {
val init = Bool(INPUT) initMap(c) = c.addPin(Bool(INPUT), "init")
init.isIo = true
init.setName("init")
init.component = c
c.io.asInstanceOf[Bundle] += init
initMap += (c -> init)
} }
transforms += collectNodesIntoComp
transforms += addTopLevelPin transforms += addTopLevelPin
transforms += addMemPin transforms += addMemPin
} }