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tilelink2: don't use chisel3 namespace (#355)

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Wesley W. Terpstra 2016-09-27 14:44:26 -07:00 committed by Andrew Waterman
parent 357d06ac9c
commit eaea138d0d
4 changed files with 4 additions and 6 deletions
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4
src/main/scala/uncore/tilelink2/Bundles.scala
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@ -2,8 +2,8 @@
package uncore.tilelink2 package uncore.tilelink2
import chisel3._ import Chisel._
import chisel3.util._ import chisel3.util.{Irrevocable, IrrevocableIO}
abstract class GenericParameterizedBundle[T <: Object](val params: T) extends Bundle abstract class GenericParameterizedBundle[T <: Object](val params: T) extends Bundle
{ {

1
src/main/scala/uncore/tilelink2/Fuzzer.scala
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@ -2,7 +2,6 @@
package uncore.tilelink2 package uncore.tilelink2
import Chisel._ import Chisel._
import chisel3.util.LFSR16
import unittest._ import unittest._
import util.Pow2ClockDivider import util.Pow2ClockDivider

1
src/main/scala/uncore/tilelink2/RAMModel.scala
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@ -3,7 +3,6 @@
package uncore.tilelink2 package uncore.tilelink2
import Chisel._ import Chisel._
import chisel3.util.LFSR16
// We detect concurrent puts that put memory into an undefined state. // We detect concurrent puts that put memory into an undefined state.
// put0, put0Ack, put1, put1Ack => ok: defined // put0, put0Ack, put1, put1Ack => ok: defined

4
src/main/scala/uncore/tilelink2/RegMapper.scala
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@ -2,8 +2,8 @@
package uncore.tilelink2 package uncore.tilelink2
import chisel3._ import Chisel._
import chisel3.util._ import chisel3.util.{Irrevocable, IrrevocableIO}
// A bus agnostic register interface to a register-based device // A bus agnostic register interface to a register-based device