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tilelink2: don't apply HintHandler to B=>C by default

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This commit is contained in:
Wesley W. Terpstra 2016-08-30 16:16:45 -07:00
parent cc8112d02e
commit eac4d44131
1 changed files with 43 additions and 23 deletions
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66
uncore/src/main/scala/tilelink2/HintHandler.scala
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@ -5,11 +5,11 @@ package uncore.tilelink2
import Chisel._ import Chisel._
// Acks Hints for managers that don't support them or Acks all Hints if !passthrough // Acks Hints for managers that don't support them or Acks all Hints if !passthrough
class TLHintHandler(passthrough: Boolean = true) extends TLSimpleFactory class TLHintHandler(supportManagers: Boolean = true, supportClients: Boolean = false, passthrough: Boolean = true) extends TLSimpleFactory
{ {
val node = TLAdapterNode( val node = TLAdapterNode(
clientFn = { case Seq(c) => c.copy(clients = c.clients .map(_.copy(supportsHint = true))) }, clientFn = { case Seq(c) => if (supportClients) c.copy(clients = c.clients .map(_.copy(supportsHint = true))) else c },
managerFn = { case Seq(m) => m.copy(managers = m.managers.map(_.copy(supportsHint = true))) }) managerFn = { case Seq(m) => if (supportManagers) m.copy(managers = m.managers.map(_.copy(supportsHint = true))) else m })
lazy val module = Module(new TLModule(this) { lazy val module = Module(new TLModule(this) {
val io = new Bundle { val io = new Bundle {
@ -22,29 +22,49 @@ class TLHintHandler(passthrough: Boolean = true) extends TLSimpleFactory
val edgeIn = node.edgesIn(0) val edgeIn = node.edgesIn(0)
val edgeOut = node.edgesOut(0) val edgeOut = node.edgesOut(0)
val handleA = if (passthrough) !edgeOut.manager.supportsHint(in.a.bits.address) else Bool(true) if (supportManagers) {
val bypassD = handleA && in.a.bits.opcode === TLMessages.Hint val handleA = if (passthrough) !edgeOut.manager.supportsHint(in.a.bits.address) else Bool(true)
val bypassD = handleA && in.a.bits.opcode === TLMessages.Hint
// Prioritize existing D traffic over HintAck // Prioritize existing D traffic over HintAck
in.d.valid := out.d.valid || (bypassD && in.a.valid) in.d.valid := out.d.valid || (bypassD && in.a.valid)
out.d.ready := in.d.ready out.d.ready := in.d.ready
in.d.bits := Mux(out.d.valid, out.d.bits, edgeIn.HintAck(in.a.bits.source, in.a.bits.size)) in.d.bits := Mux(out.d.valid, out.d.bits, edgeIn.HintAck(in.a.bits.source, in.a.bits.size))
in.a.ready := Mux(bypassD, in.d.ready && !out.d.valid, out.a.ready) in.a.ready := Mux(bypassD, in.d.ready && !out.d.valid, out.a.ready)
out.a.valid := in.a.valid && !bypassD out.a.valid := in.a.valid && !bypassD
out.a.bits := in.a.bits out.a.bits := in.a.bits
} else {
val handleB = if (passthrough) !edgeIn.client.supportsHint(out.b.bits.source) else Bool(true) out.a.valid := in.a.valid
val bypassC = handleB && out.b.bits.opcode === TLMessages.Hint in.a.ready := out.a.ready
out.a.bits := in.a.bits
// Prioritize existing C traffic over HintAck in.d.valid := out.d.valid
out.c.valid := in.c.valid || (bypassC && in.b.valid) out.d.ready := in.d.ready
in.c.ready := out.c.ready in.d.bits := out.d.bits
out.c.bits := Mux(in.c.valid, in.c.bits, edgeOut.HintAck(out.b.bits.address, out.b.bits.size)) }
out.b.ready := Mux(bypassC, out.c.ready && !in.c.valid, in.b.ready) if (supportClients) {
in.b.valid := out.b.valid && !bypassC val handleB = if (passthrough) !edgeIn.client.supportsHint(out.b.bits.source) else Bool(true)
in.b.bits := out.b.bits val bypassC = handleB && out.b.bits.opcode === TLMessages.Hint
// Prioritize existing C traffic over HintAck
out.c.valid := in.c.valid || (bypassC && in.b.valid)
in.c.ready := out.c.ready
out.c.bits := Mux(in.c.valid, in.c.bits, edgeOut.HintAck(out.b.bits.address, out.b.bits.size))
out.b.ready := Mux(bypassC, out.c.ready && !in.c.valid, in.b.ready)
in.b.valid := out.b.valid && !bypassC
in.b.bits := out.b.bits
} else {
in.b.valid := out.b.valid
out.b.ready := in.b.ready
in.b.bits := out.b.bits
out.c.valid := in.c.valid
in.c.ready := out.c.ready
out.c.bits := in.c.bits
}
// Pass E through unchanged // Pass E through unchanged
out.e.valid := in.e.valid out.e.valid := in.e.valid