RegFieldDesc: reserved omits ()

src/main/scala/devices/tilelink/Plic.scala

@@ -173,13 +173,13 @@ class TLPLIC(params: PLICParams, beatBytes: Int)(implicit p: Parameters) extends
         reset=if (nPriorities > 0) None else Some(1),
         wrType=Some(RegFieldWrType.MODIFY))
     } else {
-      RegFieldDesc.reserved()
+      RegFieldDesc.reserved
     }
     def pendingRegDesc(i: Int) = if (i > 0) {
       RegFieldDesc(s"pending_$i", s"Set to 1 if interrupt source $i is pending, regardless of its enable or priority setting.",
       volatile = true)
     } else {
-      RegFieldDesc.reserved()
+      RegFieldDesc.reserved
     }
 
     def priorityRegField(x: UInt, i: Int) = if (nPriorities > 0) RegField(32, x, priorityRegDesc(i)) else RegField.r(32, x, priorityRegDesc(i))
@@ -195,7 +195,7 @@ class TLPLIC(params: PLICParams, beatBytes: Int)(implicit p: Parameters) extends
         e.zipWithIndex.map{case (b, j) => if (j > 0) {
           RegField(1, b, RegFieldDesc(s"enable_${i}_${j}", s"Enable interrupt for source $j for target $i.", reset=None))
         } else {
-          RegField(1, b, RegFieldDesc.reserved())
+          RegField(1, b, RegFieldDesc.reserved)
         }})
     }
 

src/main/scala/regmapper/RegField.scala

@@ -47,7 +47,7 @@ case class RegFieldDesc (
 }
 
 object RegFieldDesc {
-  def reserved() RegFieldDesc = RegFieldDesc("reserved", "", access=RegFieldAccessType.R, reset=Some(0))
+  def reserved: RegFieldDesc = RegFieldDesc("reserved", "", access=RegFieldAccessType.R, reset=Some(0))
 }
 
 // Our descriptions are in terms of RegFields only, which is somewhat
@@ -145,7 +145,7 @@ object RegField
   // Byte address => sequence of bitfields, lowest index => lowest address
   type Map = (Int, Seq[RegField])
 
-  def apply(n: Int)                                                             : RegField = apply(n, (), (), Some(RegFieldDesc.reserved()))
+  def apply(n: Int)                                                             : RegField = apply(n, (), (), Some(RegFieldDesc.reserved))
 
   def apply(n: Int, r: RegReadFn, w: RegWriteFn)                                : RegField = apply(n, r,  w,  None)
   def apply(n: Int, r: RegReadFn, w: RegWriteFn, desc: RegFieldDesc)            : RegField = apply(n, r,  w,  Some(desc))

src/main/scala/rocket/BusErrorUnit.scala

@@ -63,22 +63,26 @@ class BusErrorUnit[T <: BusErrors](t: => T, params: BusErrorUnitParams)(implicit
     val enable = Reg(init = Vec(sources.map(_.nonEmpty.B)))
     val enable_desc =  sources.zipWithIndex.map { case (s, i) =>
       if (s.nonEmpty) RegFieldDesc(s"enable_$i", "", reset=Some(1))
-      else RegFieldDesc.reserved()}
+      else RegFieldDesc.reserved
+    }
 
     val global_interrupt = Reg(init = Vec.fill(sources.size)(false.B))
     val global_interrupt_desc = sources.zipWithIndex.map { case (s, i) =>
       if (s.nonEmpty) RegFieldDesc(s"plic_interrupt_$i", "", reset=Some(0))
-      else RegFieldDesc.reserved()}
+      else RegFieldDesc.reserved
+    }
 
     val accrued = Reg(init = Vec.fill(sources.size)(false.B))
     val accrued_desc = sources.zipWithIndex.map { case (s, i) =>
       if (s.nonEmpty) RegFieldDesc(s"accrued_$i", "", reset=Some(0), volatile = true)
-      else RegFieldDesc.reserved()}
+      else RegFieldDesc.reserved
+    }
 
     val local_interrupt = Reg(init = Vec.fill(sources.size)(false.B))
     val local_interrupt_desc = sources.zipWithIndex.map { case (s, i) =>
       if (s.nonEmpty) RegFieldDesc(s"local_interrupt_$i", "", reset=Some(0))
-      else RegFieldDesc.reserved()}
+      else RegFieldDesc.reserved
+    }
 
     for ((((s, en), acc), i) <- (sources zip enable zip accrued).zipWithIndex; if s.nonEmpty) {
       when (s.get.valid) {