riscv/rocket-chip
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RegFieldDesc: reserved omits ()

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This commit is contained in:
Henry Cook
2018-03-11 12:12:40 -07:00
committed by Megan Wachs
parent 15e058e3da
commit ea89259dd4
3 changed files with 13 additions and 9 deletions
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12
src/main/scala/rocket/BusErrorUnit.scala
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@ -63,22 +63,26 @@ class BusErrorUnit[T <: BusErrors](t: => T, params: BusErrorUnitParams)(implicit
val enable = Reg(init = Vec(sources.map(_.nonEmpty.B)))
val enable_desc = sources.zipWithIndex.map { case (s, i) =>
if (s.nonEmpty) RegFieldDesc(s"enable_$i", "", reset=Some(1))
else RegFieldDesc.reserved()}
else RegFieldDesc.reserved
}
val global_interrupt = Reg(init = Vec.fill(sources.size)(false.B))
val global_interrupt_desc = sources.zipWithIndex.map { case (s, i) =>
if (s.nonEmpty) RegFieldDesc(s"plic_interrupt_$i", "", reset=Some(0))
else RegFieldDesc.reserved()}
else RegFieldDesc.reserved
}
val accrued = Reg(init = Vec.fill(sources.size)(false.B))
val accrued_desc = sources.zipWithIndex.map { case (s, i) =>
if (s.nonEmpty) RegFieldDesc(s"accrued_$i", "", reset=Some(0), volatile = true)
else RegFieldDesc.reserved()}
else RegFieldDesc.reserved
}
val local_interrupt = Reg(init = Vec.fill(sources.size)(false.B))
val local_interrupt_desc = sources.zipWithIndex.map { case (s, i) =>
if (s.nonEmpty) RegFieldDesc(s"local_interrupt_$i", "", reset=Some(0))
else RegFieldDesc.reserved()}
else RegFieldDesc.reserved
}
for ((((s, en), acc), i) <- (sources zip enable zip accrued).zipWithIndex; if s.nonEmpty) {
when (s.get.valid) {