improve id/ex datapath
move operand selection into decode stage; simplify bypassing
This commit is contained in:
Andrew Waterman
parent
d471a8b2da
commit
e9da2cf66a
@ -15,14 +15,13 @@ object Constants
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val BR_J = UFix(7, 4);
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val BR_J = UFix(7, 4);
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val BR_JR = UFix(8, 4);
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val BR_JR = UFix(8, 4);
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val PC_4 = UFix(0, 4);
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val PC_4 = UFix(0, 3);
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val PC_BTB = UFix(1, 4);
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val PC_BTB = UFix(1, 3);
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val PC_EX4 = UFix(2, 4);
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val PC_EX4 = UFix(2, 3);
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val PC_BR = UFix(3, 4);
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val PC_BR = UFix(3, 3);
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val PC_JR = UFix(4, 4);
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val PC_PCR = UFix(4, 3);
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val PC_PCR = UFix(5, 4);
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val PC_WB = UFix(5, 3);
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val PC_WB = UFix(6, 4);
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val PC_EVEC = UFix(6, 3);
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val PC_EVEC = UFix(7, 4);
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val KF_Y = UFix(1, 1);
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val KF_Y = UFix(1, 1);
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val KF_N = UFix(0, 1);
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val KF_N = UFix(0, 1);
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@ -30,19 +29,13 @@ object Constants
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val REN_Y = UFix(1, 1);
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val REN_Y = UFix(1, 1);
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val REN_N = UFix(0, 1);
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val REN_N = UFix(0, 1);
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val AS_X = UFix(0, 1);
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val A2_X = UFix(0, 3);
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val AS_IMM = UFix(0, 1);
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val A2_BTYPE = UFix(0, 3);
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val AS_RS2 = UFix(1, 1);
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val A2_LTYPE = UFix(1, 3);
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val A2_ITYPE = UFix(2, 3);
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val A2_X = UFix(0, 2);
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val A2_ZERO = UFix(4, 3);
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val A2_0 = UFix(0, 2);
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val A2_JTYPE = UFix(5, 3);
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val A2_SEXT = UFix(1, 2);
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val A2_RTYPE = UFix(6, 3);
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val A2_RS2 = UFix(2, 2);
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val A2_SPLIT = UFix(3, 2);
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val A1_X = UFix(0, 1);
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val A1_RS1 = UFix(0, 1);
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val A1_LUI = UFix(1, 1);
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val MUL_X = UFix(0, 2);
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val MUL_X = UFix(0, 2);
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val MUL_LO = UFix(0, 2);
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val MUL_LO = UFix(0, 2);
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@ -94,6 +87,7 @@ object Constants
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val FN_SL = UFix(7, 4);
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val FN_SL = UFix(7, 4);
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val FN_SR = UFix(8, 4);
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val FN_SR = UFix(8, 4);
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val FN_SRA = UFix(9, 4);
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val FN_SRA = UFix(9, 4);
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val FN_OP2 = UFix(10, 4);
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val DW_X = UFix(0, 1);
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val DW_X = UFix(0, 1);
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val DW_32 = UFix(0, 1);
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val DW_32 = UFix(0, 1);
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@ -9,7 +9,7 @@ import Instructions._
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class ioCtrlDpath extends Bundle()
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class ioCtrlDpath extends Bundle()
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{
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{
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// outputs to datapath
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// outputs to datapath
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val sel_pc = UFix(4, OUTPUT);
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val sel_pc = UFix(3, OUTPUT);
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val wen_btb = Bool(OUTPUT);
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val wen_btb = Bool(OUTPUT);
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val clr_btb = Bool(OUTPUT);
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val clr_btb = Bool(OUTPUT);
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val stallf = Bool(OUTPUT);
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val stallf = Bool(OUTPUT);
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@ -20,8 +20,7 @@ class ioCtrlDpath extends Bundle()
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val killm = Bool(OUTPUT);
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val killm = Bool(OUTPUT);
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val ren2 = Bool(OUTPUT);
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val ren2 = Bool(OUTPUT);
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val ren1 = Bool(OUTPUT);
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val ren1 = Bool(OUTPUT);
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val sel_alu2 = UFix(2, OUTPUT);
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val sel_alu2 = UFix(3, OUTPUT);
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val sel_alu1 = Bool(OUTPUT);
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val fn_dw = Bool(OUTPUT);
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val fn_dw = Bool(OUTPUT);
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val fn_alu = UFix(4, OUTPUT);
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val fn_alu = UFix(4, OUTPUT);
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val mul_val = Bool(OUTPUT);
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val mul_val = Bool(OUTPUT);
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@ -39,9 +38,6 @@ class ioCtrlDpath extends Bundle()
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val ex_wen = Bool(OUTPUT);
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val ex_wen = Bool(OUTPUT);
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val mem_wen = Bool(OUTPUT);
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val mem_wen = Bool(OUTPUT);
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val wb_wen = Bool(OUTPUT);
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val wb_wen = Bool(OUTPUT);
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// instruction in execute is an unconditional jump
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val ex_jmp = Bool(OUTPUT);
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val ex_jr = Bool(OUTPUT);
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// enable/disable interrupts
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// enable/disable interrupts
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val irq_enable = Bool(OUTPUT);
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val irq_enable = Bool(OUTPUT);
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val irq_disable = Bool(OUTPUT);
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val irq_disable = Bool(OUTPUT);
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@ -103,130 +99,130 @@ class rocketCtrl extends Component
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val xpr64 = Y;
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val xpr64 = Y;
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val cs =
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val cs =
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ListLookup(io.dpath.inst,
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ListLookup(io.dpath.inst,
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List( N, BR_N, REN_N,REN_N,A2_X, A1_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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List( N, BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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Array(
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Array(
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BNE-> List(Y, BR_NE, REN_Y,REN_Y,A2_RS2, A1_RS1,DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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BNE-> List(Y, BR_NE, REN_Y,REN_Y,A2_BTYPE,DW_X, FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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ADDI-> List(Y, BR_N, REN_N,REN_Y,A2_SEXT, A1_RS1,DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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BEQ-> List(Y, BR_EQ, REN_Y,REN_Y,A2_BTYPE,DW_X, FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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BEQ-> List(Y, BR_EQ, REN_Y,REN_Y,A2_RS2, A1_RS1,DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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BLT-> List(Y, BR_LT, REN_Y,REN_Y,A2_BTYPE,DW_X, FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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BLT-> List(Y, BR_LT, REN_Y,REN_Y,A2_RS2, A1_RS1,DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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BLTU-> List(Y, BR_LTU,REN_Y,REN_Y,A2_BTYPE,DW_X, FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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BLTU-> List(Y, BR_LTU,REN_Y,REN_Y,A2_RS2, A1_RS1,DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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BGE-> List(Y, BR_GE, REN_Y,REN_Y,A2_BTYPE,DW_X, FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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BGE-> List(Y, BR_GE, REN_Y,REN_Y,A2_RS2, A1_RS1,DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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BGEU-> List(Y, BR_GEU,REN_Y,REN_Y,A2_BTYPE,DW_X, FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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BGEU-> List(Y, BR_GEU,REN_Y,REN_Y,A2_RS2, A1_RS1,DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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J-> List(Y, BR_J, REN_N,REN_N,A2_X, A1_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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J-> List(Y, BR_J, REN_N,REN_N,A2_JTYPE,DW_X, FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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JAL-> List(Y, BR_J, REN_N,REN_N,A2_X, A1_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RA,WB_PC, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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JAL-> List(Y, BR_J, REN_N,REN_N,A2_JTYPE,DW_X, FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RA,WB_PC, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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JALR_C-> List(Y, BR_JR, REN_N,REN_Y,A2_SEXT, A1_RS1,DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_PC, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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JALR_C-> List(Y, BR_JR, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_PC, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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JALR_J-> List(Y, BR_JR, REN_N,REN_Y,A2_SEXT, A1_RS1,DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_PC, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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JALR_J-> List(Y, BR_JR, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_PC, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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JALR_R-> List(Y, BR_JR, REN_N,REN_Y,A2_SEXT, A1_RS1,DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_PC, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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JALR_R-> List(Y, BR_JR, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_PC, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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RDNPC-> List(Y, BR_N, REN_N,REN_Y,A2_SEXT, A1_RS1,DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_PC, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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RDNPC-> List(Y, BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_PC, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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LB-> List(Y, BR_N, REN_N,REN_Y,A2_SEXT, A1_RS1,DW_XPR,FN_ADD, M_Y,M_XRD, MT_B, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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LB-> List(Y, BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_Y,M_XRD, MT_B, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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LH-> List(Y, BR_N, REN_N,REN_Y,A2_SEXT, A1_RS1,DW_XPR,FN_ADD, M_Y,M_XRD, MT_H, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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LH-> List(Y, BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_Y,M_XRD, MT_H, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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LW-> List(Y, BR_N, REN_N,REN_Y,A2_SEXT, A1_RS1,DW_XPR,FN_ADD, M_Y,M_XRD, MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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LW-> List(Y, BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_Y,M_XRD, MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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LD-> List(xpr64, BR_N, REN_N,REN_Y,A2_SEXT, A1_RS1,DW_XPR,FN_ADD, M_Y,M_XRD, MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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LD-> List(xpr64, BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_Y,M_XRD, MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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LBU-> List(Y, BR_N, REN_N,REN_Y,A2_SEXT, A1_RS1,DW_XPR,FN_ADD, M_Y,M_XRD, MT_BU,N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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LBU-> List(Y, BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_Y,M_XRD, MT_BU,N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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LHU-> List(Y, BR_N, REN_N,REN_Y,A2_SEXT, A1_RS1,DW_XPR,FN_ADD, M_Y,M_XRD, MT_HU,N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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LHU-> List(Y, BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_Y,M_XRD, MT_HU,N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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LWU-> List(xpr64, BR_N, REN_N,REN_Y,A2_SEXT, A1_RS1,DW_XPR,FN_ADD, M_Y,M_XRD, MT_WU,N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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LWU-> List(xpr64, BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_Y,M_XRD, MT_WU,N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SB-> List(Y, BR_N, REN_Y,REN_Y,A2_SPLIT,A1_RS1,DW_XPR,FN_ADD, M_Y,M_XWR, MT_B, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SB-> List(Y, BR_N, REN_Y,REN_Y,A2_BTYPE,DW_XPR,FN_ADD, M_Y,M_XWR, MT_B, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SH-> List(Y, BR_N, REN_Y,REN_Y,A2_SPLIT,A1_RS1,DW_XPR,FN_ADD, M_Y,M_XWR, MT_H, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SH-> List(Y, BR_N, REN_Y,REN_Y,A2_BTYPE,DW_XPR,FN_ADD, M_Y,M_XWR, MT_H, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SW-> List(Y, BR_N, REN_Y,REN_Y,A2_SPLIT,A1_RS1,DW_XPR,FN_ADD, M_Y,M_XWR, MT_W, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SW-> List(Y, BR_N, REN_Y,REN_Y,A2_BTYPE,DW_XPR,FN_ADD, M_Y,M_XWR, MT_W, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SD-> List(xpr64, BR_N, REN_Y,REN_Y,A2_SPLIT,A1_RS1,DW_XPR,FN_ADD, M_Y,M_XWR, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SD-> List(xpr64, BR_N, REN_Y,REN_Y,A2_BTYPE,DW_XPR,FN_ADD, M_Y,M_XWR, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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AMOADD_W-> List(Y, BR_N, REN_Y,REN_Y,A2_0, A1_RS1,DW_XPR,FN_ADD, M_Y,M_XA_ADD, MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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AMOADD_W-> List(Y, BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_ADD, MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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AMOSWAP_W->List(Y, BR_N, REN_Y,REN_Y,A2_0, A1_RS1,DW_XPR,FN_ADD, M_Y,M_XA_SWAP,MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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AMOSWAP_W->List(Y, BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_SWAP,MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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AMOAND_W-> List(Y, BR_N, REN_Y,REN_Y,A2_0, A1_RS1,DW_XPR,FN_ADD, M_Y,M_XA_AND, MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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AMOAND_W-> List(Y, BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_AND, MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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AMOOR_W-> List(Y, BR_N, REN_Y,REN_Y,A2_0, A1_RS1,DW_XPR,FN_ADD, M_Y,M_XA_OR, MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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AMOOR_W-> List(Y, BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_OR, MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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AMOMIN_W-> List(Y, BR_N, REN_Y,REN_Y,A2_0, A1_RS1,DW_XPR,FN_ADD, M_Y,M_XA_MIN, MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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AMOMIN_W-> List(Y, BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_MIN, MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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AMOMINU_W->List(Y, BR_N, REN_Y,REN_Y,A2_0, A1_RS1,DW_XPR,FN_ADD, M_Y,M_XA_MINU,MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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AMOMINU_W->List(Y, BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_MINU,MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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AMOMAX_W-> List(Y, BR_N, REN_Y,REN_Y,A2_0, A1_RS1,DW_XPR,FN_ADD, M_Y,M_XA_MAX, MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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AMOMAX_W-> List(Y, BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_MAX, MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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AMOMAXU_W->List(Y, BR_N, REN_Y,REN_Y,A2_0, A1_RS1,DW_XPR,FN_ADD, M_Y,M_XA_MAXU,MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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AMOMAXU_W->List(Y, BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_MAXU,MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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AMOADD_D-> List(xpr64, BR_N, REN_Y,REN_Y,A2_0, A1_RS1,DW_XPR,FN_ADD, M_Y,M_XA_ADD, MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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AMOADD_D-> List(xpr64, BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_ADD, MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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AMOSWAP_D->List(xpr64, BR_N, REN_Y,REN_Y,A2_0, A1_RS1,DW_XPR,FN_ADD, M_Y,M_XA_SWAP,MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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AMOSWAP_D->List(xpr64, BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_SWAP,MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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AMOAND_D-> List(xpr64, BR_N, REN_Y,REN_Y,A2_0, A1_RS1,DW_XPR,FN_ADD, M_Y,M_XA_AND, MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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AMOAND_D-> List(xpr64, BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_AND, MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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AMOOR_D-> List(xpr64, BR_N, REN_Y,REN_Y,A2_0, A1_RS1,DW_XPR,FN_ADD, M_Y,M_XA_OR, MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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AMOOR_D-> List(xpr64, BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_OR, MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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AMOMIN_D-> List(xpr64, BR_N, REN_Y,REN_Y,A2_0, A1_RS1,DW_XPR,FN_ADD, M_Y,M_XA_MIN, MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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AMOMIN_D-> List(xpr64, BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_MIN, MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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AMOMINU_D->List(xpr64, BR_N, REN_Y,REN_Y,A2_0, A1_RS1,DW_XPR,FN_ADD, M_Y,M_XA_MINU,MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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AMOMINU_D->List(xpr64, BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_MINU,MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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AMOMAX_D-> List(xpr64, BR_N, REN_Y,REN_Y,A2_0, A1_RS1,DW_XPR,FN_ADD, M_Y,M_XA_MAX, MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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AMOMAX_D-> List(xpr64, BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_MAX, MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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AMOMAXU_D->List(xpr64, BR_N, REN_Y,REN_Y,A2_0, A1_RS1,DW_XPR,FN_ADD, M_Y,M_XA_MAXU,MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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AMOMAXU_D->List(xpr64, BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_MAXU,MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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LUI-> List(Y, BR_N, REN_N,REN_Y,A2_0, A1_LUI,DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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LUI-> List(Y, BR_N, REN_N,REN_N,A2_LTYPE,DW_XPR,FN_OP2, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SLTI -> List(Y, BR_N, REN_N,REN_Y,A2_SEXT, A1_RS1,DW_XPR,FN_SLT, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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ADDI-> List(Y, BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SLTIU-> List(Y, BR_N, REN_N,REN_Y,A2_SEXT, A1_RS1,DW_XPR,FN_SLTU,M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SLTI -> List(Y, BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_SLT, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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ANDI-> List(Y, BR_N, REN_N,REN_Y,A2_SEXT, A1_RS1,DW_XPR,FN_AND, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SLTIU-> List(Y, BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_SLTU,M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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ORI-> List(Y, BR_N, REN_N,REN_Y,A2_SEXT, A1_RS1,DW_XPR,FN_OR, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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ANDI-> List(Y, BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_AND, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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XORI-> List(Y, BR_N, REN_N,REN_Y,A2_SEXT, A1_RS1,DW_XPR,FN_XOR, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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ORI-> List(Y, BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_OR, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SLLI-> List(Y, BR_N, REN_N,REN_Y,A2_SEXT, A1_RS1,DW_XPR,FN_SL, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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XORI-> List(Y, BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_XOR, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SRLI-> List(Y_SH, BR_N, REN_N,REN_Y,A2_SEXT, A1_RS1,DW_XPR,FN_SR, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SLLI-> List(Y, BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_SL, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SRAI-> List(Y_SH, BR_N, REN_N,REN_Y,A2_SEXT, A1_RS1,DW_XPR,FN_SRA, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SRLI-> List(Y_SH, BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_SR, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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ADD-> List(Y, BR_N, REN_Y,REN_Y,A2_RS2, A1_RS1,DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SRAI-> List(Y_SH, BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_SRA, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SUB-> List(Y, BR_N, REN_Y,REN_Y,A2_RS2, A1_RS1,DW_XPR,FN_SUB, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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ADD-> List(Y, BR_N, REN_Y,REN_Y,A2_RTYPE,DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SLT-> List(Y, BR_N, REN_Y,REN_Y,A2_RS2, A1_RS1,DW_XPR,FN_SLT, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SUB-> List(Y, BR_N, REN_Y,REN_Y,A2_RTYPE,DW_XPR,FN_SUB, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SLTU-> List(Y, BR_N, REN_Y,REN_Y,A2_RS2, A1_RS1,DW_XPR,FN_SLTU,M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SLT-> List(Y, BR_N, REN_Y,REN_Y,A2_RTYPE,DW_XPR,FN_SLT, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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riscvAND-> List(Y, BR_N, REN_Y,REN_Y,A2_RS2, A1_RS1,DW_XPR,FN_AND, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SLTU-> List(Y, BR_N, REN_Y,REN_Y,A2_RTYPE,DW_XPR,FN_SLTU,M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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riscvOR-> List(Y, BR_N, REN_Y,REN_Y,A2_RS2, A1_RS1,DW_XPR,FN_OR, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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riscvAND-> List(Y, BR_N, REN_Y,REN_Y,A2_RTYPE,DW_XPR,FN_AND, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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riscvXOR-> List(Y, BR_N, REN_Y,REN_Y,A2_RS2, A1_RS1,DW_XPR,FN_XOR, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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riscvOR-> List(Y, BR_N, REN_Y,REN_Y,A2_RTYPE,DW_XPR,FN_OR, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SLL-> List(Y, BR_N, REN_Y,REN_Y,A2_RS2, A1_RS1,DW_XPR,FN_SL, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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riscvXOR-> List(Y, BR_N, REN_Y,REN_Y,A2_RTYPE,DW_XPR,FN_XOR, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SRL-> List(Y, BR_N, REN_Y,REN_Y,A2_RS2, A1_RS1,DW_XPR,FN_SR, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SLL-> List(Y, BR_N, REN_Y,REN_Y,A2_RTYPE,DW_XPR,FN_SL, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SRA-> List(Y, BR_N, REN_Y,REN_Y,A2_RS2, A1_RS1,DW_XPR,FN_SRA, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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SRL-> List(Y, BR_N, REN_Y,REN_Y,A2_RTYPE,DW_XPR,FN_SR, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
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||||||
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SRA-> List(Y, BR_N, REN_Y,REN_Y,A2_RTYPE,DW_XPR,FN_SRA, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
||||||
|
|
||||||
ADDIW-> List(xpr64, BR_N, REN_N,REN_Y,A2_SEXT, A1_RS1,DW_32,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
ADDIW-> List(xpr64, BR_N, REN_N,REN_Y,A2_ITYPE,DW_32,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
||||||
SLLIW-> List(xpr64, BR_N, REN_N,REN_Y,A2_SEXT, A1_RS1,DW_32,FN_SL, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
SLLIW-> List(xpr64, BR_N, REN_N,REN_Y,A2_ITYPE,DW_32,FN_SL, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
||||||
SRLIW-> List(xpr64, BR_N, REN_N,REN_Y,A2_SEXT, A1_RS1,DW_32,FN_SR, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
SRLIW-> List(xpr64, BR_N, REN_N,REN_Y,A2_ITYPE,DW_32,FN_SR, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
||||||
SRAIW-> List(xpr64, BR_N, REN_N,REN_Y,A2_SEXT, A1_RS1,DW_32,FN_SRA, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
SRAIW-> List(xpr64, BR_N, REN_N,REN_Y,A2_ITYPE,DW_32,FN_SRA, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
||||||
ADDW-> List(xpr64, BR_N, REN_Y,REN_Y,A2_RS2, A1_RS1,DW_32,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
ADDW-> List(xpr64, BR_N, REN_Y,REN_Y,A2_RTYPE,DW_32,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
||||||
SUBW-> List(xpr64, BR_N, REN_Y,REN_Y,A2_RS2, A1_RS1,DW_32,FN_SUB, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
SUBW-> List(xpr64, BR_N, REN_Y,REN_Y,A2_RTYPE,DW_32,FN_SUB, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
||||||
SLLW-> List(xpr64, BR_N, REN_Y,REN_Y,A2_RS2, A1_RS1,DW_32,FN_SL, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
SLLW-> List(xpr64, BR_N, REN_Y,REN_Y,A2_RTYPE,DW_32,FN_SL, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
||||||
SRLW-> List(xpr64, BR_N, REN_Y,REN_Y,A2_RS2, A1_RS1,DW_32,FN_SR, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
SRLW-> List(xpr64, BR_N, REN_Y,REN_Y,A2_RTYPE,DW_32,FN_SR, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
||||||
SRAW-> List(xpr64, BR_N, REN_Y,REN_Y,A2_RS2, A1_RS1,DW_32,FN_SRA, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
SRAW-> List(xpr64, BR_N, REN_Y,REN_Y,A2_RTYPE,DW_32,FN_SRA, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
||||||
|
|
||||||
MUL-> List(Y, BR_N, REN_Y,REN_Y,A2_X, A1_X, DW_XPR,FN_X, M_N,M_X, MT_X, Y,MUL_LO, N,DIV_X, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
MUL-> List(Y, BR_N, REN_Y,REN_Y,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, Y,MUL_LO, N,DIV_X, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
||||||
MULH-> List(Y, BR_N, REN_Y,REN_Y,A2_X, A1_X, DW_XPR,FN_X, M_N,M_X, MT_X, Y,MUL_HS, N,DIV_X, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
MULH-> List(Y, BR_N, REN_Y,REN_Y,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, Y,MUL_HS, N,DIV_X, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
||||||
MULHU-> List(Y, BR_N, REN_Y,REN_Y,A2_X, A1_X, DW_XPR,FN_X, M_N,M_X, MT_X, Y,MUL_HU, N,DIV_X, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
MULHU-> List(Y, BR_N, REN_Y,REN_Y,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, Y,MUL_HU, N,DIV_X, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
||||||
MULHSU-> List(Y, BR_N, REN_Y,REN_Y,A2_X, A1_X, DW_XPR,FN_X, M_N,M_X, MT_X, Y,MUL_HSU, N,DIV_X, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
MULHSU-> List(Y, BR_N, REN_Y,REN_Y,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, Y,MUL_HSU, N,DIV_X, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
||||||
MULW-> List(xpr64, BR_N, REN_Y,REN_Y,A2_X, A1_X, DW_32, FN_X, M_N,M_X, MT_X, Y,MUL_LO, N,DIV_X, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
MULW-> List(xpr64, BR_N, REN_Y,REN_Y,A2_X, DW_32, FN_X, M_N,M_X, MT_X, Y,MUL_LO, N,DIV_X, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
||||||
|
|
||||||
DIV-> List(Y, BR_N, REN_Y,REN_Y,A2_X, A1_X, DW_XPR,FN_X, M_N,M_X, MT_X, N,MUL_X, Y,DIV_D, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
DIV-> List(Y, BR_N, REN_Y,REN_Y,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, N,MUL_X, Y,DIV_D, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
||||||
DIVU-> List(Y, BR_N, REN_Y,REN_Y,A2_X, A1_X, DW_XPR,FN_X, M_N,M_X, MT_X, N,MUL_X, Y,DIV_DU, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
DIVU-> List(Y, BR_N, REN_Y,REN_Y,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, N,MUL_X, Y,DIV_DU, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
||||||
REM-> List(Y, BR_N, REN_Y,REN_Y,A2_X, A1_X, DW_XPR,FN_X, M_N,M_X, MT_X, N,MUL_X, Y,DIV_R, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
REM-> List(Y, BR_N, REN_Y,REN_Y,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, N,MUL_X, Y,DIV_R, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
||||||
REMU-> List(Y, BR_N, REN_Y,REN_Y,A2_X, A1_X, DW_XPR,FN_X, M_N,M_X, MT_X, N,MUL_X, Y,DIV_RU, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
REMU-> List(Y, BR_N, REN_Y,REN_Y,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, N,MUL_X, Y,DIV_RU, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
||||||
DIVW-> List(xpr64, BR_N, REN_Y,REN_Y,A2_X, A1_X, DW_32, FN_X, M_N,M_X, MT_X, N,MUL_X, Y,DIV_D, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
DIVW-> List(xpr64, BR_N, REN_Y,REN_Y,A2_X, DW_32, FN_X, M_N,M_X, MT_X, N,MUL_X, Y,DIV_D, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
||||||
DIVUW-> List(xpr64, BR_N, REN_Y,REN_Y,A2_X, A1_X, DW_32, FN_X, M_N,M_X, MT_X, N,MUL_X, Y,DIV_DU, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
DIVUW-> List(xpr64, BR_N, REN_Y,REN_Y,A2_X, DW_32, FN_X, M_N,M_X, MT_X, N,MUL_X, Y,DIV_DU, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
||||||
REMW-> List(xpr64, BR_N, REN_Y,REN_Y,A2_X, A1_X, DW_32, FN_X, M_N,M_X, MT_X, N,MUL_X, Y,DIV_R, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
REMW-> List(xpr64, BR_N, REN_Y,REN_Y,A2_X, DW_32, FN_X, M_N,M_X, MT_X, N,MUL_X, Y,DIV_R, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
||||||
REMUW-> List(xpr64, BR_N, REN_Y,REN_Y,A2_X, A1_X, DW_32, FN_X, M_N,M_X, MT_X, N,MUL_X, Y,DIV_RU, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
REMUW-> List(xpr64, BR_N, REN_Y,REN_Y,A2_X, DW_32, FN_X, M_N,M_X, MT_X, N,MUL_X, Y,DIV_RU, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
||||||
|
|
||||||
SYSCALL-> List(Y, BR_N, REN_N,REN_N,A2_X, A1_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,Y,N,N),
|
SYSCALL-> List(Y, BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,Y,N,N),
|
||||||
EI-> List(Y, BR_N, REN_N,REN_N,A2_X, A1_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_EI,SYNC_N,N,N,Y,Y),
|
EI-> List(Y, BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_EI,SYNC_N,N,N,Y,Y),
|
||||||
DI-> List(Y, BR_N, REN_N,REN_N,A2_X, A1_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_DI,SYNC_N,N,N,Y,Y),
|
DI-> List(Y, BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_DI,SYNC_N,N,N,Y,Y),
|
||||||
ERET-> List(Y, BR_N, REN_N,REN_N,A2_X, A1_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_PCR,REN_N,WEN_N,I_X ,SYNC_N,Y,N,Y,N),
|
ERET-> List(Y, BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_PCR,REN_N,WEN_N,I_X ,SYNC_N,Y,N,Y,N),
|
||||||
FENCE-> List(Y, BR_N, REN_N,REN_N,A2_X, A1_X, DW_X, FN_X, M_Y,M_FENCE, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_D,N,N,N,N),
|
FENCE-> List(Y, BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_Y,M_FENCE, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_D,N,N,N,N),
|
||||||
FENCE_I-> List(Y, BR_N, REN_N,REN_N,A2_X, A1_X, DW_X, FN_X, M_Y,M_FLA, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_I,N,N,N,N),
|
FENCE_I-> List(Y, BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_Y,M_FLA, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_I,N,N,N,N),
|
||||||
CFLUSH-> List(Y, BR_N, REN_Y,REN_N,A2_X, A1_X, DW_X, FN_X, M_Y,M_FLA, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,Y,Y),
|
CFLUSH-> List(Y, BR_N, REN_Y,REN_N,A2_X, DW_X, FN_X, M_Y,M_FLA, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,Y,Y),
|
||||||
MFPCR-> List(Y, BR_N, REN_N,REN_N,A2_X, A1_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_PCR,REN_Y,WEN_N,I_X ,SYNC_N,N,N,Y,N),
|
MFPCR-> List(Y, BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_PCR,REN_Y,WEN_N,I_X ,SYNC_N,N,N,Y,N),
|
||||||
MTPCR-> List(Y, BR_N, REN_N,REN_Y,A2_X, A1_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_Y,I_X ,SYNC_N,N,N,Y,Y),
|
MTPCR-> List(Y, BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_Y,I_X ,SYNC_N,N,N,Y,Y),
|
||||||
RDTIME-> List(Y, BR_N, REN_N,REN_Y,A2_SEXT, A1_RS1,DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_TSC,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
RDTIME-> List(Y, BR_N, REN_N,REN_N,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_TSC,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
||||||
RDCYCLE-> List(Y, BR_N, REN_N,REN_Y,A2_SEXT, A1_RS1,DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_TSC,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
RDCYCLE-> List(Y, BR_N, REN_N,REN_N,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_TSC,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
||||||
RDINSTRET->List(Y, BR_N, REN_N,REN_Y,A2_SEXT, A1_RS1,DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_IRT,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
RDINSTRET->List(Y, BR_N, REN_N,REN_N,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_IRT,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
||||||
|
|
||||||
// Instructions that have not yet been implemented
|
// Instructions that have not yet been implemented
|
||||||
// Faking these for now so akaros will boot
|
// Faking these for now so akaros will boot
|
||||||
//MFFSR-> List(Y, BR_N, REN_N,REN_N,A2_X, A1_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
//MFFSR-> List(Y, BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
||||||
//MTFSR-> List(Y, BR_N, REN_N,REN_N,A2_X, A1_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
//MTFSR-> List(Y, BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
||||||
FLW-> List(Y, BR_N, REN_N,REN_Y,A2_SEXT, A1_RS1,DW_XPR,FN_ADD, M_Y,M_XRD, MT_W, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
FLW-> List(Y, BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_Y,M_XRD, MT_W, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
||||||
FLD-> List(Y, BR_N, REN_N,REN_Y,A2_SEXT, A1_RS1,DW_XPR,FN_ADD, M_Y,M_XRD, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
FLD-> List(Y, BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_Y,M_XRD, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
||||||
FSW-> List(Y, BR_N, REN_N,REN_Y,A2_SPLIT,A1_RS1,DW_XPR,FN_ADD, M_Y,M_XWR, MT_W, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
FSW-> List(Y, BR_N, REN_N,REN_Y,A2_BTYPE,DW_XPR,FN_ADD, M_Y,M_XWR, MT_W, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
|
||||||
FSD-> List(Y, BR_N, REN_N,REN_Y,A2_SPLIT,A1_RS1,DW_XPR,FN_ADD, M_Y,M_XWR, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N)
|
FSD-> List(Y, BR_N, REN_N,REN_Y,A2_BTYPE,DW_XPR,FN_ADD, M_Y,M_XWR, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N)
|
||||||
/*
|
/*
|
||||||
// floating point
|
// floating point
|
||||||
FLW-> List(FPU_Y, BR_N, REN_N,REN_Y,A2_SEXT, A1_RS1,DW_XPR,FN_ADD, M_Y,M_FRD, MT_WU,N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
|
FLW-> List(FPU_Y, BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_Y,M_FRD, MT_WU,N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
|
||||||
FLD-> List(FPU_Y, BR_N, REN_N,REN_Y,A2_SEXT, A1_RS1,DW_XPR,FN_ADD, M_Y,M_FRD, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
|
FLD-> List(FPU_Y, BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_Y,M_FRD, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
|
||||||
FSW-> List(FPU_Y, BR_N, REN_Y,REN_Y,A2_SPLIT,A1_RS1,DW_XPR,FN_ADD, M_Y,M_FWR, MT_W, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
|
FSW-> List(FPU_Y, BR_N, REN_Y,REN_Y,A2_BTYPE,DW_XPR,FN_ADD, M_Y,M_FWR, MT_W, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
|
||||||
FSD-> List(FPU_Y, BR_N, REN_Y,REN_Y,A2_SPLIT,A1_RS1,DW_XPR,FN_ADD, M_Y,M_FWR, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
|
FSD-> List(FPU_Y, BR_N, REN_Y,REN_Y,A2_BTYPE,DW_XPR,FN_ADD, M_Y,M_FWR, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
|
||||||
*/
|
*/
|
||||||
));
|
));
|
||||||
|
|
||||||
val if_reg_xcpt_ma_inst = Reg(io.dpath.xcpt_ma_inst, resetVal = Bool(false));
|
val if_reg_xcpt_ma_inst = Reg(io.dpath.xcpt_ma_inst, resetVal = Bool(false));
|
||||||
|
|
||||||
val id_int_val :: id_br_type :: id_renx2 :: id_renx1 :: id_sel_alu2 :: id_sel_alu1 :: id_fn_dw :: id_fn_alu :: csremainder = cs;
|
val id_int_val :: id_br_type :: id_renx2 :: id_renx1 :: id_sel_alu2 :: id_fn_dw :: id_fn_alu :: csremainder = cs;
|
||||||
val id_mem_val :: id_mem_cmd :: id_mem_type :: id_mul_val :: id_mul_fn :: id_div_val :: id_div_fn :: id_wen :: id_sel_wa :: id_sel_wb :: id_ren_pcr :: id_wen_pcr :: id_irq :: id_sync :: id_eret :: id_syscall :: id_privileged :: id_replay_next :: Nil = csremainder;
|
val id_mem_val :: id_mem_cmd :: id_mem_type :: id_mul_val :: id_mul_fn :: id_div_val :: id_div_fn :: id_wen :: id_sel_wa :: id_sel_wb :: id_ren_pcr :: id_wen_pcr :: id_irq :: id_sync :: id_eret :: id_syscall :: id_privileged :: id_replay_next :: Nil = csremainder;
|
||||||
|
|
||||||
val id_raddr3 = io.dpath.inst(16,12);
|
val id_raddr3 = io.dpath.inst(16,12);
|
||||||
@ -360,12 +356,6 @@ class rocketCtrl extends Component
|
|||||||
ex_reg_mem_cmd <== id_mem_cmd;
|
ex_reg_mem_cmd <== id_mem_cmd;
|
||||||
ex_reg_mem_type <== id_mem_type;
|
ex_reg_mem_type <== id_mem_type;
|
||||||
|
|
||||||
|
|
||||||
val jr_taken = (ex_reg_br_type === BR_JR);
|
|
||||||
val j_taken = (ex_reg_br_type === BR_J);
|
|
||||||
io.dpath.ex_jmp := j_taken;
|
|
||||||
io.dpath.ex_jr := jr_taken;
|
|
||||||
|
|
||||||
val beq = io.dpath.br_eq;
|
val beq = io.dpath.br_eq;
|
||||||
val bne = ~io.dpath.br_eq;
|
val bne = ~io.dpath.br_eq;
|
||||||
val blt = io.dpath.br_lt;
|
val blt = io.dpath.br_lt;
|
||||||
@ -380,7 +370,8 @@ class rocketCtrl extends Component
|
|||||||
(ex_reg_br_type === BR_LTU) & bltu |
|
(ex_reg_br_type === BR_LTU) & bltu |
|
||||||
(ex_reg_br_type === BR_GE) & bge |
|
(ex_reg_br_type === BR_GE) & bge |
|
||||||
(ex_reg_br_type === BR_GEU) & bgeu |
|
(ex_reg_br_type === BR_GEU) & bgeu |
|
||||||
j_taken; // treat J/JAL like a taken branch
|
(ex_reg_br_type === BR_J) |
|
||||||
|
(ex_reg_br_type === BR_JR); // treat J/JAL/JALR like a taken branch
|
||||||
|
|
||||||
val mem_reg_div_mul_val = Reg(){Bool()};
|
val mem_reg_div_mul_val = Reg(){Bool()};
|
||||||
val mem_reg_eret = Reg(){Bool()};
|
val mem_reg_eret = Reg(){Bool()};
|
||||||
@ -526,8 +517,7 @@ class rocketCtrl extends Component
|
|||||||
|
|
||||||
// control transfer from ex/mem
|
// control transfer from ex/mem
|
||||||
val ex_btb_match = ex_reg_btb_hit && io.dpath.btb_match
|
val ex_btb_match = ex_reg_btb_hit && io.dpath.btb_match
|
||||||
val br_jr_taken = br_taken || jr_taken
|
val take_pc_ex = !ex_btb_match && br_taken || ex_reg_btb_hit && !br_taken
|
||||||
val take_pc_ex = !ex_btb_match && br_jr_taken || ex_reg_btb_hit && !br_jr_taken
|
|
||||||
val take_pc_wb = wb_reg_replay || wb_reg_exception || wb_reg_eret;
|
val take_pc_wb = wb_reg_replay || wb_reg_exception || wb_reg_eret;
|
||||||
take_pc <== take_pc_ex || take_pc_wb;
|
take_pc <== take_pc_ex || take_pc_wb;
|
||||||
|
|
||||||
@ -563,14 +553,13 @@ class rocketCtrl extends Component
|
|||||||
Mux(wb_reg_exception, PC_EVEC, // exception
|
Mux(wb_reg_exception, PC_EVEC, // exception
|
||||||
Mux(wb_reg_replay, PC_WB, // replay
|
Mux(wb_reg_replay, PC_WB, // replay
|
||||||
Mux(wb_reg_eret, PC_PCR, // eret instruction
|
Mux(wb_reg_eret, PC_PCR, // eret instruction
|
||||||
Mux(ex_reg_btb_hit && !br_jr_taken, PC_EX4, // mispredicted not taken branch
|
Mux(ex_reg_btb_hit && !br_taken, PC_EX4, // mispredicted not taken branch
|
||||||
Mux(!ex_btb_match && br_taken, PC_BR, // mispredicted taken branch
|
Mux(!ex_btb_match && br_taken, PC_BR, // mispredicted taken branch
|
||||||
Mux(!ex_btb_match && jr_taken, PC_JR, // mispredicted jump register
|
|
||||||
Mux(io.dpath.btb_hit, PC_BTB, // predicted PC from BTB
|
Mux(io.dpath.btb_hit, PC_BTB, // predicted PC from BTB
|
||||||
PC_4))))))); // PC+4
|
PC_4)))))); // PC+4
|
||||||
|
|
||||||
io.dpath.wen_btb := !ex_btb_match && br_jr_taken;
|
io.dpath.wen_btb := !ex_btb_match && br_taken;
|
||||||
io.dpath.clr_btb := ex_reg_btb_hit && !br_jr_taken || id_reg_icmiss;
|
io.dpath.clr_btb := ex_reg_btb_hit && !br_taken || id_reg_icmiss;
|
||||||
|
|
||||||
io.imem.req_val := take_pc_wb || !mem_reg_replay && !ex_reg_replay && (take_pc_ex || !id_reg_replay)
|
io.imem.req_val := take_pc_wb || !mem_reg_replay && !ex_reg_replay && (take_pc_ex || !id_reg_replay)
|
||||||
|
|
||||||
@ -645,7 +634,6 @@ class rocketCtrl extends Component
|
|||||||
io.dpath.ren2 := id_renx2.toBool;
|
io.dpath.ren2 := id_renx2.toBool;
|
||||||
io.dpath.ren1 := id_renx1.toBool;
|
io.dpath.ren1 := id_renx1.toBool;
|
||||||
io.dpath.sel_alu2 := id_sel_alu2;
|
io.dpath.sel_alu2 := id_sel_alu2;
|
||||||
io.dpath.sel_alu1 := id_sel_alu1.toBool;
|
|
||||||
io.dpath.fn_dw := id_fn_dw.toBool;
|
io.dpath.fn_dw := id_fn_dw.toBool;
|
||||||
io.dpath.fn_alu := id_fn_alu;
|
io.dpath.fn_alu := id_fn_alu;
|
||||||
io.dpath.div_fn := id_div_fn;
|
io.dpath.div_fn := id_div_fn;
|
||||||
|
|||||||
@ -75,13 +75,11 @@ class rocketDpath extends Component
|
|||||||
// execute definitions
|
// execute definitions
|
||||||
val ex_reg_valid = Reg(resetVal = Bool(false));
|
val ex_reg_valid = Reg(resetVal = Bool(false));
|
||||||
val ex_reg_pc = Reg() { UFix() };
|
val ex_reg_pc = Reg() { UFix() };
|
||||||
val ex_reg_inst = Reg() { Bits() };
|
|
||||||
val ex_reg_raddr2 = Reg() { UFix() };
|
val ex_reg_raddr2 = Reg() { UFix() };
|
||||||
|
val ex_reg_op2 = Reg() { Bits() };
|
||||||
val ex_reg_rs2 = Reg() { Bits() };
|
val ex_reg_rs2 = Reg() { Bits() };
|
||||||
val ex_reg_rs1 = Reg() { Bits() };
|
val ex_reg_rs1 = Reg() { Bits() };
|
||||||
val ex_reg_waddr = Reg() { UFix() };
|
val ex_reg_waddr = Reg() { UFix() };
|
||||||
val ex_reg_ctrl_sel_alu2 = Reg() { UFix() };
|
|
||||||
val ex_reg_ctrl_sel_alu1 = Reg() { UFix() };
|
|
||||||
val ex_reg_ctrl_eret = Reg(resetVal = Bool(false));
|
val ex_reg_ctrl_eret = Reg(resetVal = Bool(false));
|
||||||
val ex_reg_ctrl_fn_dw = Reg() { UFix() };
|
val ex_reg_ctrl_fn_dw = Reg() { UFix() };
|
||||||
val ex_reg_ctrl_fn_alu = Reg() { UFix() };
|
val ex_reg_ctrl_fn_alu = Reg() { UFix() };
|
||||||
@ -124,31 +122,23 @@ class rocketDpath extends Component
|
|||||||
val if_pc_plus4 = if_reg_pc + UFix(4);
|
val if_pc_plus4 = if_reg_pc + UFix(4);
|
||||||
|
|
||||||
val ex_pc_plus4 = ex_reg_pc + UFix(4);
|
val ex_pc_plus4 = ex_reg_pc + UFix(4);
|
||||||
val ex_sign_extend =
|
val ex_branch_target = ex_reg_pc + Cat(ex_reg_op2, Bits(0,1)).toUFix
|
||||||
Cat(Fill(52, ex_reg_inst(21)), ex_reg_inst(21,10));
|
|
||||||
val ex_sign_extend_split =
|
|
||||||
Cat(Fill(52, ex_reg_inst(31)), ex_reg_inst(31,27), ex_reg_inst(16,10));
|
|
||||||
|
|
||||||
val branch_adder_rhs =
|
val ex_ea_sign = Mux(ex_alu_adder_out(VADDR_BITS-1), ~ex_alu_adder_out(63,VADDR_BITS) === UFix(0), ex_alu_adder_out(63,VADDR_BITS) != UFix(0))
|
||||||
Mux(io.ctrl.ex_jmp, Cat(Fill(VADDR_BITS-25, ex_reg_inst(31)), ex_reg_inst(31,7), UFix(0,1)),
|
val ex_effective_address = Cat(ex_ea_sign, ex_alu_adder_out(VADDR_BITS-1,0)).toUFix
|
||||||
Cat(ex_sign_extend_split(VADDR_BITS-1,0), UFix(0, 1)));
|
|
||||||
val ex_branch_target = ex_reg_pc + branch_adder_rhs.toUFix;
|
|
||||||
|
|
||||||
val ex_jr_target_sign = Mux(ex_alu_adder_out(VADDR_BITS-1), ~ex_alu_adder_out(63,VADDR_BITS) === UFix(0), ex_alu_adder_out(63,VADDR_BITS) != UFix(0))
|
val ex_br_target_sel = Reg(io.ctrl.sel_alu2 === A2_BTYPE || io.ctrl.sel_alu2 === A2_JTYPE)
|
||||||
val ex_jr_target_extended = Cat(ex_jr_target_sign, ex_alu_adder_out(VADDR_BITS-1,0)).toUFix
|
val ex_br_target = Mux(ex_br_target_sel, ex_branch_target, ex_effective_address)
|
||||||
|
btb.io.correct_target := ex_br_target
|
||||||
val jr_br_target = Mux(io.ctrl.ex_jr, ex_jr_target_extended, ex_branch_target);
|
|
||||||
btb.io.correct_target := jr_br_target
|
|
||||||
|
|
||||||
val if_next_pc =
|
val if_next_pc =
|
||||||
Mux(io.ctrl.sel_pc === PC_BTB, Cat(if_btb_target(VADDR_BITS-1), if_btb_target),
|
Mux(io.ctrl.sel_pc === PC_BTB, Cat(if_btb_target(VADDR_BITS-1), if_btb_target),
|
||||||
Mux(io.ctrl.sel_pc === PC_EX4, ex_pc_plus4,
|
Mux(io.ctrl.sel_pc === PC_EX4, ex_pc_plus4,
|
||||||
Mux(io.ctrl.sel_pc === PC_BR, ex_branch_target,
|
Mux(io.ctrl.sel_pc === PC_BR, ex_br_target,
|
||||||
Mux(io.ctrl.sel_pc === PC_JR, ex_jr_target_extended,
|
|
||||||
Mux(io.ctrl.sel_pc === PC_PCR, wb_reg_wdata(VADDR_BITS,0), // only used for ERET
|
Mux(io.ctrl.sel_pc === PC_PCR, wb_reg_wdata(VADDR_BITS,0), // only used for ERET
|
||||||
Mux(io.ctrl.sel_pc === PC_EVEC, Cat(pcr.io.evec(VADDR_BITS-1), pcr.io.evec),
|
Mux(io.ctrl.sel_pc === PC_EVEC, Cat(pcr.io.evec(VADDR_BITS-1), pcr.io.evec),
|
||||||
Mux(io.ctrl.sel_pc === PC_WB, wb_reg_pc,
|
Mux(io.ctrl.sel_pc === PC_WB, wb_reg_pc,
|
||||||
if_pc_plus4))))))); // PC_4
|
if_pc_plus4)))))); // PC_4
|
||||||
|
|
||||||
when (!io.ctrl.stallf) {
|
when (!io.ctrl.stallf) {
|
||||||
if_reg_pc <== if_next_pc.toUFix;
|
if_reg_pc <== if_next_pc.toUFix;
|
||||||
@ -165,7 +155,7 @@ class rocketDpath extends Component
|
|||||||
btb.io.wen <> io.ctrl.wen_btb;
|
btb.io.wen <> io.ctrl.wen_btb;
|
||||||
btb.io.clr <> io.ctrl.clr_btb;
|
btb.io.clr <> io.ctrl.clr_btb;
|
||||||
btb.io.correct_pc4 := ex_pc_plus4;
|
btb.io.correct_pc4 := ex_pc_plus4;
|
||||||
io.ctrl.btb_match := id_reg_pc === jr_br_target;
|
io.ctrl.btb_match := id_reg_pc === ex_br_target;
|
||||||
|
|
||||||
// instruction decode stage
|
// instruction decode stage
|
||||||
when (!io.ctrl.stalld) {
|
when (!io.ctrl.stalld) {
|
||||||
@ -210,17 +200,33 @@ class rocketDpath extends Component
|
|||||||
Mux((io.ctrl.wb_wen || wb_reg_ll_wb) && id_raddr2 === wb_reg_waddr, wb_wdata,
|
Mux((io.ctrl.wb_wen || wb_reg_ll_wb) && id_raddr2 === wb_reg_waddr, wb_wdata,
|
||||||
id_rdata2)));
|
id_rdata2)));
|
||||||
|
|
||||||
|
// immediate generation
|
||||||
|
val id_imm_bj = io.ctrl.sel_alu2 === A2_BTYPE || io.ctrl.sel_alu2 === A2_JTYPE
|
||||||
|
val id_imm_l = io.ctrl.sel_alu2 === A2_LTYPE
|
||||||
|
val id_imm_zero = io.ctrl.sel_alu2 === A2_ZERO || io.ctrl.sel_alu2 === A2_RTYPE
|
||||||
|
val id_imm_ibz = io.ctrl.sel_alu2 === A2_ITYPE || io.ctrl.sel_alu2 === A2_BTYPE || id_imm_zero
|
||||||
|
val id_imm_sign = Mux(id_imm_bj, id_reg_inst(31),
|
||||||
|
Mux(id_imm_l, id_reg_inst(26),
|
||||||
|
Mux(id_imm_zero, Bits(0,1),
|
||||||
|
id_reg_inst(21)))) // IMM_ITYPE
|
||||||
|
val id_imm_small = Mux(id_imm_zero, Bits(0,12),
|
||||||
|
Cat(Mux(id_imm_bj, id_reg_inst(31,27), id_reg_inst(21,17)), id_reg_inst(16,10)))
|
||||||
|
val id_imm = Cat(Fill(32, id_imm_sign),
|
||||||
|
Mux(id_imm_l, Cat(id_reg_inst(26,7), Bits(0,12)),
|
||||||
|
Mux(id_imm_ibz, Cat(Fill(20, id_imm_sign), id_imm_small),
|
||||||
|
Cat(Fill(7, id_imm_sign), id_reg_inst(31,7))))) // A2_JTYPE
|
||||||
|
|
||||||
|
val id_op2 = Mux(io.ctrl.sel_alu2 === A2_RTYPE, id_rs2, id_imm)
|
||||||
|
|
||||||
io.ctrl.inst := id_reg_inst;
|
io.ctrl.inst := id_reg_inst;
|
||||||
|
|
||||||
// execute stage
|
// execute stage
|
||||||
ex_reg_pc <== id_reg_pc;
|
ex_reg_pc <== id_reg_pc;
|
||||||
ex_reg_inst <== id_reg_inst;
|
|
||||||
ex_reg_raddr2 <== id_raddr2;
|
ex_reg_raddr2 <== id_raddr2;
|
||||||
|
ex_reg_op2 <== id_op2;
|
||||||
ex_reg_rs2 <== id_rs2;
|
ex_reg_rs2 <== id_rs2;
|
||||||
ex_reg_rs1 <== id_rs1;
|
ex_reg_rs1 <== id_rs1;
|
||||||
ex_reg_waddr <== id_waddr;
|
ex_reg_waddr <== id_waddr;
|
||||||
ex_reg_ctrl_sel_alu2 <== io.ctrl.sel_alu2;
|
|
||||||
ex_reg_ctrl_sel_alu1 <== io.ctrl.sel_alu1.toUFix;
|
|
||||||
ex_reg_ctrl_fn_dw <== io.ctrl.fn_dw.toUFix;
|
ex_reg_ctrl_fn_dw <== io.ctrl.fn_dw.toUFix;
|
||||||
ex_reg_ctrl_fn_alu <== io.ctrl.fn_alu;
|
ex_reg_ctrl_fn_alu <== io.ctrl.fn_alu;
|
||||||
ex_reg_ctrl_mul_fn <== io.ctrl.mul_fn;
|
ex_reg_ctrl_mul_fn <== io.ctrl.mul_fn;
|
||||||
@ -243,24 +249,10 @@ class rocketDpath extends Component
|
|||||||
ex_reg_ctrl_eret <== io.ctrl.id_eret;
|
ex_reg_ctrl_eret <== io.ctrl.id_eret;
|
||||||
}
|
}
|
||||||
|
|
||||||
val ex_alu_in2 =
|
|
||||||
Mux(ex_reg_ctrl_sel_alu2 === A2_SEXT, ex_sign_extend,
|
|
||||||
Mux(ex_reg_ctrl_sel_alu2 === A2_SPLIT, ex_sign_extend_split,
|
|
||||||
Mux(ex_reg_ctrl_sel_alu2 === A2_RS2, ex_reg_rs2,
|
|
||||||
UFix(0, 64)))); // A2_0
|
|
||||||
|
|
||||||
val ex_alu_in1 =
|
|
||||||
Mux(ex_reg_ctrl_sel_alu1 === A1_RS1, ex_reg_rs1,
|
|
||||||
Cat(Fill(32, ex_reg_inst(26)),ex_reg_inst(26,7),UFix(0, 12))); // A1_LUI
|
|
||||||
|
|
||||||
val ex_alu_shamt =
|
|
||||||
Cat(ex_alu_in2(5) & ex_reg_ctrl_fn_dw === DW_64, ex_alu_in2(4,0)).toUFix;
|
|
||||||
|
|
||||||
alu.io.dw := ex_reg_ctrl_fn_dw;
|
alu.io.dw := ex_reg_ctrl_fn_dw;
|
||||||
alu.io.fn := ex_reg_ctrl_fn_alu;
|
alu.io.fn := ex_reg_ctrl_fn_alu;
|
||||||
alu.io.shamt := ex_alu_shamt.toUFix;
|
alu.io.in2 := ex_reg_op2.toUFix;
|
||||||
alu.io.in2 := ex_alu_in2.toUFix;
|
alu.io.in1 := ex_reg_rs1.toUFix;
|
||||||
alu.io.in1 := ex_alu_in1.toUFix;
|
|
||||||
|
|
||||||
// divider
|
// divider
|
||||||
div.io.dw := ex_reg_ctrl_fn_dw;
|
div.io.dw := ex_reg_ctrl_fn_dw;
|
||||||
@ -292,7 +284,7 @@ class rocketDpath extends Component
|
|||||||
|
|
||||||
// D$ request interface (registered inside D$ module)
|
// D$ request interface (registered inside D$ module)
|
||||||
// other signals (req_val, req_rdy) connect to control module
|
// other signals (req_val, req_rdy) connect to control module
|
||||||
io.dmem.req_addr := ex_jr_target_extended.toUFix;
|
io.dmem.req_addr := ex_effective_address.toUFix;
|
||||||
if (HAVE_FPU) {
|
if (HAVE_FPU) {
|
||||||
io.dmem.req_data := Mux(io.ctrl.ex_fp_val, io.fpu.store_data, ex_reg_rs2)
|
io.dmem.req_data := Mux(io.ctrl.ex_fp_val, io.fpu.store_data, ex_reg_rs2)
|
||||||
io.dmem.req_tag := Cat(ex_reg_waddr, io.ctrl.ex_fp_val).toUFix
|
io.dmem.req_tag := Cat(ex_reg_waddr, io.ctrl.ex_fp_val).toUFix
|
||||||
@ -335,12 +327,11 @@ class rocketDpath extends Component
|
|||||||
|
|
||||||
// writeback select mux
|
// writeback select mux
|
||||||
ex_wdata :=
|
ex_wdata :=
|
||||||
Mux(ex_reg_ctrl_wen_pcr, ex_reg_rs1,
|
|
||||||
Mux(ex_reg_ctrl_sel_wb === WB_PC, Cat(Fill(64-VADDR_BITS, ex_pc_plus4(VADDR_BITS-1)), ex_pc_plus4),
|
Mux(ex_reg_ctrl_sel_wb === WB_PC, Cat(Fill(64-VADDR_BITS, ex_pc_plus4(VADDR_BITS-1)), ex_pc_plus4),
|
||||||
Mux(ex_reg_ctrl_sel_wb === WB_PCR, ex_pcr,
|
Mux(ex_reg_ctrl_sel_wb === WB_PCR, ex_pcr,
|
||||||
Mux(ex_reg_ctrl_sel_wb === WB_TSC, tsc_reg,
|
Mux(ex_reg_ctrl_sel_wb === WB_TSC, tsc_reg,
|
||||||
Mux(ex_reg_ctrl_sel_wb === WB_IRT, irt_reg,
|
Mux(ex_reg_ctrl_sel_wb === WB_IRT, irt_reg,
|
||||||
ex_alu_out))))).toBits; // WB_ALU
|
ex_alu_out)))).toBits; // WB_ALU
|
||||||
|
|
||||||
// memory stage
|
// memory stage
|
||||||
mem_reg_pc <== ex_reg_pc;
|
mem_reg_pc <== ex_reg_pc;
|
||||||
|
|||||||
@ -10,7 +10,6 @@ import Instructions._
|
|||||||
class ioALU extends Bundle(){
|
class ioALU extends Bundle(){
|
||||||
val dw = UFix(1, INPUT);
|
val dw = UFix(1, INPUT);
|
||||||
val fn = UFix(4, INPUT);
|
val fn = UFix(4, INPUT);
|
||||||
val shamt = UFix(6, INPUT);
|
|
||||||
val in2 = UFix(64, INPUT);
|
val in2 = UFix(64, INPUT);
|
||||||
val in1 = UFix(64, INPUT);
|
val in1 = UFix(64, INPUT);
|
||||||
val out = UFix(64, OUTPUT);
|
val out = UFix(64, OUTPUT);
|
||||||
@ -27,31 +26,31 @@ class rocketDpathALU extends Component
|
|||||||
val sum = (io.in1 + adder_rhs + sub.toUFix)(63,0)
|
val sum = (io.in1 + adder_rhs + sub.toUFix)(63,0)
|
||||||
|
|
||||||
// SLT, SLTU
|
// SLT, SLTU
|
||||||
val less = Mux(io.in1(63) === io.in2(63), sum(63), io.in1(63))
|
val less = Mux(io.in1(63) === io.in2(63), sum(63),
|
||||||
val lessu = Mux(io.in1(63) === io.in2(63), sum(63), io.in2(63))
|
Mux(io.fn === FN_SLT, io.in1(63), io.in2(63)))
|
||||||
|
|
||||||
// SLL, SRL, SRA
|
// SLL, SRL, SRA
|
||||||
val sra = (io.fn === FN_SRA)
|
val sra = (io.fn === FN_SRA)
|
||||||
|
val shamt = Cat(io.in2(5) & (io.dw === DW_64), io.in2(4,0)).toUFix
|
||||||
val shright = sra || (io.fn === FN_SR)
|
val shright = sra || (io.fn === FN_SR)
|
||||||
val shin_hi_32 = Mux(sra, Fill(32, io.in1(31)), UFix(0,32))
|
val shin_hi_32 = Mux(sra, Fill(32, io.in1(31)), UFix(0,32))
|
||||||
val shin_hi = Mux(io.dw === DW_64, io.in1(63,32), shin_hi_32)
|
val shin_hi = Mux(io.dw === DW_64, io.in1(63,32), shin_hi_32)
|
||||||
val shin_r = Cat(shin_hi, io.in1(31,0))
|
val shin_r = Cat(shin_hi, io.in1(31,0))
|
||||||
val shin = Mux(shright, shin_r, Reverse(shin_r))
|
val shin = Mux(shright, shin_r, Reverse(shin_r))
|
||||||
val shout_r = (Cat(sra & shin_r(63), shin).toFix >>> io.shamt)(63,0)
|
val shout_r = (Cat(sra & shin_r(63), shin).toFix >>> shamt)(63,0)
|
||||||
|
|
||||||
val out64 = Wire { Bits(64) }
|
val logic =
|
||||||
switch(io.fn)
|
Mux(io.fn === FN_AND, io.in1 & io.in2,
|
||||||
{
|
Mux(io.fn === FN_OR, io.in1 | io.in2,
|
||||||
is(FN_ADD) { out64 <== sum }
|
Mux(io.fn === FN_XOR, io.in1 ^ io.in2,
|
||||||
is(FN_SUB) { out64 <== sum }
|
io.in2))) // FN_OP2
|
||||||
is(FN_SLT) { out64 <== less }
|
|
||||||
is(FN_SLTU) { out64 <== lessu }
|
val out64 =
|
||||||
is(FN_AND) { out64 <== io.in1 & io.in2 }
|
Mux(io.fn === FN_ADD || io.fn === FN_SUB, sum,
|
||||||
is(FN_OR) { out64 <== io.in1 | io.in2 }
|
Mux(io.fn === FN_SLT || io.fn === FN_SLTU, less,
|
||||||
is(FN_XOR) { out64 <== io.in1 ^ io.in2 }
|
Mux(io.fn === FN_SR || io.fn === FN_SRA, shout_r,
|
||||||
is(FN_SL) { out64 <== Reverse(shout_r) }
|
Mux(io.fn === FN_SL, Reverse(shout_r),
|
||||||
}
|
logic))))
|
||||||
out64 <== shout_r
|
|
||||||
|
|
||||||
val out_hi = Mux(io.dw === DW_64, out64(63,32), Fill(32, out64(31)))
|
val out_hi = Mux(io.dw === DW_64, out64(63,32), Fill(32, out64(31)))
|
||||||
io.out := Cat(out_hi, out64(31,0)).toUFix
|
io.out := Cat(out_hi, out64(31,0)).toUFix
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user