riscv/rocket-chip
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cleanup scratchpad nodes

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This commit is contained in:
Henry Cook 2017-04-27 14:02:05 -07:00
parent b2b4725522
commit e99fa057ac
3 changed files with 23 additions and 22 deletions
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19
src/main/scala/rocket/Frontend.scala
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@ -45,21 +45,18 @@ class FrontendIO(implicit p: Parameters) extends CoreBundle()(p) {
class Frontend(hartid: Int)(implicit p: Parameters) extends LazyModule {
lazy val module = new FrontendModule(this)
val icache = LazyModule(new ICache(latency = 2, hartid))
val node = TLOutputNode()
val slaveNode = icache.slaveNode.map { n =>
val res = TLInputNode()
n := res
res
}
val masterNode = TLOutputNode()
val slaveNode = TLInputNode()
node := icache.node
icache.slaveNode.map { _ := slaveNode }
masterNode := icache.masterNode
}
class FrontendBundle(outer: Frontend) extends CoreBundle()(outer.p) {
val cpu = new FrontendIO().flip
val ptw = new TLBPTWIO()
val tl_out = outer.node.bundleOut
val tl_in = outer.slaveNode.map(_.bundleIn)
val tl_out = outer.masterNode.bundleOut
val tl_in = outer.slaveNode.bundleIn
val resetVector = UInt(INPUT, vaddrBitsExtended)
val hartid = UInt(INPUT, hartIdLen)
}
@ -68,7 +65,7 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
with HasCoreParameters
with HasL1ICacheParameters {
val io = new FrontendBundle(outer)
implicit val edge = outer.node.edgesOut(0)
implicit val edge = outer.masterNode.edgesOut.head
val icache = outer.icache.module
val tlb = Module(new TLB(log2Ceil(coreInstBytes*fetchWidth), nTLBEntries))
@ -186,7 +183,7 @@ trait HasICacheFrontend extends CanHavePTW with HasTileLinkMasterPort {
val module: HasICacheFrontendModule
val frontend = LazyModule(new Frontend(hartid: Int))
val hartid: Int
masterNode := frontend.node
masterNode := frontend.masterNode
nPTWPorts += 1
}

6
src/main/scala/rocket/ICache.scala
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@ -35,7 +35,7 @@ class ICacheReq(implicit p: Parameters) extends CoreBundle()(p) with HasL1ICache
class ICache(val latency: Int, val hartid: Int)(implicit p: Parameters) extends LazyModule
with HasRocketCoreParameters {
lazy val module = new ICacheModule(this)
val node = TLClientNode(TLClientParameters(sourceId = IdRange(0,1)))
val masterNode = TLClientNode(TLClientParameters(sourceId = IdRange(0,1)))
val icacheParams = tileParams.icache.get
val size = icacheParams.nSets * icacheParams.nWays * icacheParams.blockBytes
@ -64,7 +64,7 @@ class ICacheBundle(outer: ICache) extends CoreBundle()(outer.p) {
val resp = Valid(UInt(width = coreInstBits * fetchWidth))
val invalidate = Bool(INPUT)
val tl_out = outer.node.bundleOut
val tl_out = outer.masterNode.bundleOut
val tl_in = outer.slaveNode.map(_.bundleIn)
}
@ -78,7 +78,7 @@ object GetPropertyByHartId {
class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
with HasL1ICacheParameters {
val io = new ICacheBundle(outer)
val edge_out = outer.node.edgesOut.head
val edge_out = outer.masterNode.edgesOut.head
val tl_out = io.tl_out.head
val edge_in = outer.slaveNode.map(_.edgesIn.head)
val tl_in = io.tl_in.map(_.head)

20
src/main/scala/rocket/ScratchpadSlavePort.scala
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@ -108,18 +108,22 @@ class ScratchpadSlavePort(address: AddressSet)(implicit p: Parameters) extends L
trait CanHaveScratchpad extends HasHellaCache with HasICacheFrontend with HasCoreParameters {
val module: CanHaveScratchpadModule
val slaveNode = TLInputNode() // Up to two uses for this input node:
// 1) Frontend always exists, but may or may not have a scratchpad node
val fg = LazyModule(new TLFragmenter(fetchWidth*coreInstBytes, p(CacheBlockBytes), true))
val ww = LazyModule(new TLWidthWidget(xLen/8))
frontend.slaveNode :*= ww.node
ww.node :*= fg.node
fg.node :*= slaveNode
// 2) ScratchpadSlavePort always has a node, but only exists when the HellaCache has a scratchpad
val scratch = tileParams.dcache.flatMap(d => d.scratch.map(s =>
LazyModule(new ScratchpadSlavePort(AddressSet(s, d.dataScratchpadBytes-1)))))
val slaveNode = TLInputNode()
scratch foreach { lm => lm.node := TLFragmenter(p(XLen)/8, p(CacheBlockBytes))(slaveNode) }
frontend.slaveNode foreach { _ :=
TLFragmenter(fetchWidth*coreInstBytes, p(CacheBlockBytes), true)(
TLWidthWidget(p(XLen)/8)(slaveNode))
}
scratch foreach { lm => lm.node := TLFragmenter(xLen/8, p(CacheBlockBytes))(slaveNode) }
def findScratchpadFromICache: Option[AddressSet] = scratch.map { s =>
val finalNode = frontend.node.edgesOut(0).manager.managers.find(_.nodePath.last == s.node)
val finalNode = frontend.masterNode.edgesOut.head.manager.managers.find(_.nodePath.last == s.node)
require (finalNode.isDefined, "Could not find the scratch pad; not reachable via icache?")
require (finalNode.get.address.size == 1, "Scratchpad address space was fragmented!")
finalNode.get.address(0)