riscv/rocket-chip
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cleanup scratchpad nodes

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This commit is contained in:
Henry Cook
2017-04-27 14:02:05 -07:00
parent b2b4725522
commit e99fa057ac
3 changed files with 23 additions and 22 deletions
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20
src/main/scala/rocket/ScratchpadSlavePort.scala
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@ -108,18 +108,22 @@ class ScratchpadSlavePort(address: AddressSet)(implicit p: Parameters) extends L
trait CanHaveScratchpad extends HasHellaCache with HasICacheFrontend with HasCoreParameters {
val module: CanHaveScratchpadModule
val slaveNode = TLInputNode() // Up to two uses for this input node:
// 1) Frontend always exists, but may or may not have a scratchpad node
val fg = LazyModule(new TLFragmenter(fetchWidth*coreInstBytes, p(CacheBlockBytes), true))
val ww = LazyModule(new TLWidthWidget(xLen/8))
frontend.slaveNode :*= ww.node
ww.node :*= fg.node
fg.node :*= slaveNode
// 2) ScratchpadSlavePort always has a node, but only exists when the HellaCache has a scratchpad
val scratch = tileParams.dcache.flatMap(d => d.scratch.map(s =>
LazyModule(new ScratchpadSlavePort(AddressSet(s, d.dataScratchpadBytes-1)))))
val slaveNode = TLInputNode()
scratch foreach { lm => lm.node := TLFragmenter(p(XLen)/8, p(CacheBlockBytes))(slaveNode) }
frontend.slaveNode foreach { _ :=
TLFragmenter(fetchWidth*coreInstBytes, p(CacheBlockBytes), true)(
TLWidthWidget(p(XLen)/8)(slaveNode))
}
scratch foreach { lm => lm.node := TLFragmenter(xLen/8, p(CacheBlockBytes))(slaveNode) }
def findScratchpadFromICache: Option[AddressSet] = scratch.map { s =>
val finalNode = frontend.node.edgesOut(0).manager.managers.find(_.nodePath.last == s.node)
val finalNode = frontend.masterNode.edgesOut.head.manager.managers.find(_.nodePath.last == s.node)
require (finalNode.isDefined, "Could not find the scratch pad; not reachable via icache?")
require (finalNode.get.address.size == 1, "Scratchpad address space was fragmented!")
finalNode.get.address(0)