cleanup scratchpad nodes
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@ -35,7 +35,7 @@ class ICacheReq(implicit p: Parameters) extends CoreBundle()(p) with HasL1ICache
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class ICache(val latency: Int, val hartid: Int)(implicit p: Parameters) extends LazyModule
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with HasRocketCoreParameters {
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lazy val module = new ICacheModule(this)
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val node = TLClientNode(TLClientParameters(sourceId = IdRange(0,1)))
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val masterNode = TLClientNode(TLClientParameters(sourceId = IdRange(0,1)))
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val icacheParams = tileParams.icache.get
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val size = icacheParams.nSets * icacheParams.nWays * icacheParams.blockBytes
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@ -64,7 +64,7 @@ class ICacheBundle(outer: ICache) extends CoreBundle()(outer.p) {
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val resp = Valid(UInt(width = coreInstBits * fetchWidth))
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val invalidate = Bool(INPUT)
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val tl_out = outer.node.bundleOut
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val tl_out = outer.masterNode.bundleOut
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val tl_in = outer.slaveNode.map(_.bundleIn)
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}
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@ -78,7 +78,7 @@ object GetPropertyByHartId {
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class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
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with HasL1ICacheParameters {
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val io = new ICacheBundle(outer)
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val edge_out = outer.node.edgesOut.head
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val edge_out = outer.masterNode.edgesOut.head
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val tl_out = io.tl_out.head
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val edge_in = outer.slaveNode.map(_.edgesIn.head)
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val tl_in = io.tl_in.map(_.head)
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