riscv/rocket-chip
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integrating ITLB & PTW

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This commit is contained in:
Rimas Avizienis
2011-11-09 14:52:17 -08:00
parent 7130edac8d
commit e96430d862
11 changed files with 538 additions and 63 deletions
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3
rocket/src/main/scala/ctrl.scala
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@ -53,7 +53,7 @@ class ioCtrlDpath extends Bundle()
val mem_waddr = UFix(5,'input); // write addr from memory stage
val wb_waddr = UFix(5,'input); // write addr from writeback stage
val exception = Bool('input);
val status = Bits(8, 'input);
val status = Bits(17, 'input);
val sboard_clr0 = Bool('input);
val sboard_clr0a = UFix(5, 'input);
val sboard_clr1 = Bool('input);
@ -67,6 +67,7 @@ class ioCtrlAll extends Bundle()
val imem = new ioImem(List("req_val", "req_rdy", "resp_val")).flip();
val dmem = new ioDmem(List("req_val", "req_rdy", "req_cmd", "req_type", "resp_miss", "resp_val")).flip();
val host = new ioHost(List("start"));
// val itlb_xcpt = Bool('input);
}
class rocketCtrl extends Component