riscv/rocket-chip
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integrating ITLB & PTW

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This commit is contained in:
Rimas Avizienis
2011-11-09 14:52:17 -08:00
parent 7130edac8d
commit e96430d862
11 changed files with 538 additions and 63 deletions
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51
rocket/src/main/scala/cpu.scala
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@ -1,6 +1,6 @@
package Top {
import Chisel._
import Chisel._;
import Node._;
import Constants._;
@ -41,21 +41,60 @@ class ioRocket extends Bundle()
class rocketProc extends Component
{
val io = new ioRocket();
val ctrl = new rocketCtrl();
val dpath = new rocketDpath();
val itlb = new rocketITLB(ITLB_ENTRIES);
val ptw = new rocketPTW();
val arb = new rocketDmemArbiter();
ctrl.io.dpath <> dpath.io.ctrl;
ctrl.io.dmem ^^ io.dmem;
// ctrl.io.dmem ^^ io.dmem;
ctrl.io.host.start ^^ io.host.start;
ctrl.io.imem ^^ io.imem;
// ctrl.io.imem ^^ io.imem;
dpath.io.dmem ^^ io.dmem;
dpath.io.imem.req_addr ^^ io.imem.req_addr;
// dpath.io.dmem ^^ io.dmem;
// dpath.io.imem.req_addr ^^ io.imem.req_addr;
dpath.io.imem.resp_data ^^ io.imem.resp_data;
dpath.io.host ^^ io.host;
dpath.io.debug ^^ io.debug;
itlb.io.cpu.invalidate := Bool(false);
itlb.io.cpu.status := dpath.io.ctrl.status;
itlb.io.cpu.req_val := ctrl.io.imem.req_val;
ctrl.io.imem.req_rdy := itlb.io.cpu.req_rdy && io.imem.req_rdy;
itlb.io.cpu.req_asid := Bits(0,ASID_BITS); // FIXME: connect to PCR
itlb.io.cpu.req_vpn := dpath.io.imem.req_addr(VADDR_BITS-1,PGIDX_BITS);
io.imem.req_val := itlb.io.cpu.resp_val;
io.imem.req_addr := Cat(itlb.io.cpu.resp_ppn, dpath.io.imem.req_addr(PGIDX_BITS-1,0)).toUFix;
ctrl.io.imem.resp_val := io.imem.resp_val;
dpath.io.itlb_xcpt := itlb.io.cpu.exception;
ptw.io.itlb <> itlb.io.ptw;
ptw.io.ptbr := dpath.io.ptbr;
arb.io.ptw <> ptw.io.dmem;
arb.io.mem ^^ io.dmem
arb.io.cpu.req_val := ctrl.io.dmem.req_val;
arb.io.cpu.req_cmd := ctrl.io.dmem.req_cmd;
arb.io.cpu.req_type := ctrl.io.dmem.req_type;
arb.io.cpu.req_addr := dpath.io.dmem.req_addr;
arb.io.cpu.req_data := dpath.io.dmem.req_data;
arb.io.cpu.req_tag := dpath.io.dmem.req_tag;
ctrl.io.dmem.req_rdy := arb.io.cpu.req_rdy;
ctrl.io.dmem.resp_miss := arb.io.cpu.resp_miss;
ctrl.io.dmem.resp_val := arb.io.cpu.resp_val;
dpath.io.dmem.resp_val := arb.io.cpu.resp_val;
dpath.io.dmem.resp_tag := arb.io.cpu.resp_tag;
dpath.io.dmem.resp_data := arb.io.cpu.resp_data;
// FIXME: console disconnected
// io.console.bits := dpath.io.dpath.rs1(7,0);
io.console.bits := Bits(0,8);