integrating ITLB & PTW
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@ -128,6 +128,7 @@ object Constants
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val M_FRD = Bits("b0010", 4); // fp load
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val M_FWR = Bits("b0011", 4); // fp store
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val M_FLA = Bits("b0100", 4); // flush cache
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val M_PRD = Bits("b0101", 4); // PTW load
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val M_XA_ADD = Bits("b1000", 4);
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val M_XA_SWAP = Bits("b1001", 4);
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val M_XA_AND = Bits("b1010", 4);
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@ -145,12 +146,26 @@ object Constants
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val PCR_COMPARE = UFix( 5, 5);
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val PCR_CAUSE = UFix( 6, 5);
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val PCR_MEMSIZE = UFix( 8, 5);
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val PCR_PTBR = UFix( 9, 5);
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val PCR_LOG = UFix(10, 5);
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val PCR_TOHOST = UFix(16, 5);
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val PCR_FROMHOST = UFix(17, 5);
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val PCR_CONSOLE = UFix(18, 5);
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val PCR_K0 = UFix(24, 5);
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val PCR_K1 = UFix(25, 5);
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val PADDR_BITS = 40;
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val VADDR_BITS = 43;
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val PGIDX_BITS = 13;
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val PPN_BITS = PADDR_BITS-PGIDX_BITS;
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val VPN_BITS = VADDR_BITS-PGIDX_BITS;
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val ASID_BITS = 7;
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val PERM_BITS = 6;
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val ITLB_ENTRIES = 8;
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val HAVE_FPU = Bool(false);
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val HAVE_VEC = Bool(false);
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}
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}
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}
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