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Merge branch 'master' into riscv-tools-on-priv-1.10

This commit is contained in:
Henry Cook 2017-03-30 22:31:29 -07:00 committed by GitHub
commit e92eaa7156
4 changed files with 8 additions and 24 deletions

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@ -26,9 +26,9 @@ class DCacheDataArray(implicit p: Parameters) extends L1HellaCacheModule()(p) {
val resp = Vec(nWays, Bits(OUTPUT, rowBits)) val resp = Vec(nWays, Bits(OUTPUT, rowBits))
} }
val data_arrays = Seq.fill(nWays) { SeqMem(nSets*refillCycles, Vec(rowBytes, Bits(width=8))) }
val addr = io.req.bits.addr >> rowOffBits val addr = io.req.bits.addr >> rowOffBits
for (w <- 0 until nWays) { for ((array, w) <- data_arrays zipWithIndex) {
val array = SeqMem(nSets*refillCycles, Vec(rowBytes, Bits(width=8)))
val valid = io.req.valid && (Bool(nWays == 1) || io.req.bits.way_en(w)) val valid = io.req.valid && (Bool(nWays == 1) || io.req.bits.way_en(w))
when (valid && io.req.bits.write) { when (valid && io.req.bits.write) {
val data = Vec.tabulate(rowBytes)(i => io.req.bits.wdata(8*(i+1)-1, 8*i)) val data = Vec.tabulate(rowBytes)(i => io.req.bits.wdata(8*(i+1)-1, 8*i))

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@ -20,7 +20,6 @@ case class DCacheParams(
nWays: Int = 4, nWays: Int = 4,
rowBits: Int = 64, rowBits: Int = 64,
nTLBEntries: Int = 32, nTLBEntries: Int = 32,
splitMetadata: Boolean = false,
ecc: Option[Code] = None, ecc: Option[Code] = None,
nMSHRs: Int = 1, nMSHRs: Int = 1,
nSDQ: Int = 17, nSDQ: Int = 17,
@ -246,23 +245,11 @@ class L1MetadataArray[T <: L1Metadata](onReset: () => T)(implicit p: Parameters)
when (rst) { rst_cnt := rst_cnt+UInt(1) } when (rst) { rst_cnt := rst_cnt+UInt(1) }
val metabits = rstVal.getWidth val metabits = rstVal.getWidth
val tag_array = SeqMem(nSets, Vec(nWays, UInt(width = metabits)))
if (hasSplitMetadata) {
val tag_arrs = List.fill(nWays){ SeqMem(nSets, UInt(width = metabits)) }
val tag_readout = Wire(Vec(nWays,rstVal.cloneType))
(0 until nWays).foreach { (i) =>
when (rst || (io.write.valid && wmask(i))) {
tag_arrs(i).write(waddr, wdata)
}
io.resp(i) := rstVal.fromBits(tag_arrs(i).read(io.read.bits.idx, io.read.valid && rmask(i)))
}
} else {
val tag_arr = SeqMem(nSets, Vec(nWays, UInt(width = metabits)))
when (rst || io.write.valid) { when (rst || io.write.valid) {
tag_arr.write(waddr, Vec.fill(nWays)(wdata), wmask) tag_array.write(waddr, Vec.fill(nWays)(wdata), wmask)
}
io.resp := tag_arr.read(io.read.bits.idx, io.read.valid).map(rstVal.fromBits(_))
} }
io.resp := tag_array.read(io.read.bits.idx, io.read.valid).map(rstVal.fromBits(_))
io.read.ready := !rst && !io.write.valid // so really this could be a 6T RAM io.read.ready := !rst && !io.write.valid // so really this could be a 6T RAM
io.write.ready := !rst io.write.ready := !rst

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@ -18,7 +18,6 @@ case class ICacheParams(
rowBits: Int = 128, rowBits: Int = 128,
nTLBEntries: Int = 32, nTLBEntries: Int = 32,
cacheIdBits: Int = 0, cacheIdBits: Int = 0,
splitMetadata: Boolean = false,
ecc: Option[Code] = None, ecc: Option[Code] = None,
blockBytes: Int = 64) extends L1CacheParams { blockBytes: Int = 64) extends L1CacheParams {
def replacement = new RandomReplacement(nWays) def replacement = new RandomReplacement(nWays)
@ -128,8 +127,8 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
} }
s1_any_tag_hit := s1_tag_hit.reduceLeft(_||_) && !s1_disparity.reduceLeft(_||_) s1_any_tag_hit := s1_tag_hit.reduceLeft(_||_) && !s1_disparity.reduceLeft(_||_)
for (i <- 0 until nWays) { val data_arrays = Seq.fill(nWays) { SeqMem(nSets * refillCycles, Bits(width = code.width(rowBits))) }
val data_array = SeqMem(nSets * refillCycles, Bits(width = code.width(rowBits))) for ((data_array, i) <- data_arrays zipWithIndex) {
val wen = tl_out.d.valid && repl_way === UInt(i) val wen = tl_out.d.valid && repl_way === UInt(i)
when (wen) { when (wen) {
val e_d = code.encode(tl_out.d.bits.data) val e_d = code.encode(tl_out.d.bits.data)

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@ -15,7 +15,6 @@ trait L1CacheParams {
def nWays: Int def nWays: Int
def rowBits: Int def rowBits: Int
def nTLBEntries: Int def nTLBEntries: Int
def splitMetadata: Boolean
def ecc: Option[Code] def ecc: Option[Code]
def blockBytes: Int def blockBytes: Int
} }
@ -39,7 +38,6 @@ trait HasL1CacheParameters {
def rowOffBits = log2Up(rowBytes) def rowOffBits = log2Up(rowBytes)
def code = cacheParams.ecc.getOrElse(new IdentityCode) def code = cacheParams.ecc.getOrElse(new IdentityCode)
def nTLBEntries = cacheParams.nTLBEntries def nTLBEntries = cacheParams.nTLBEntries
def hasSplitMetadata = cacheParams.splitMetadata
def cacheDataBits = p(SharedMemoryTLEdge).bundle.dataBits def cacheDataBits = p(SharedMemoryTLEdge).bundle.dataBits
def cacheDataBeats = (cacheBlockBytes * 8) / cacheDataBits def cacheDataBeats = (cacheBlockBytes * 8) / cacheDataBits