riscv/rocket-chip
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Default mtvec=0, not None

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Setting it to None was a mistake.  It makes it far harder to
diagnose boot bugs, as you end up fetching from random addreses
after trapping.
This commit is contained in:
Andrew Waterman 2016-09-29 13:52:41 -07:00
parent 1e43512142
commit e928b741ce
1 changed files with 1 additions and 1 deletions
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src/main/scala/coreplex/Configs.scala
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@ -100,7 +100,7 @@ class BaseCoreplexConfig extends Config (
case UseCompressed => true
case DMKey => new DefaultDebugModuleConfig(site(NTiles), site(XLen))
case NCustomMRWCSRs => 0
case MtvecInit => None
case MtvecInit => Some(BigInt(0))
case MtvecWritable => true
//Uncore Paramters
case LNEndpoints => site(TLKey(site(TLId))).nManagers + site(TLKey(site(TLId))).nClients