Heterogeneous Tiles (#550)
Fundamental new features: * Added tile package: This package is intended to hold components re-usable across different types of tile. Will be the future location of TL2-RoCC accelerators and new diplomatic versions of intra-tile interfaces. * Adopted [ModuleName]Params convention: Code base was very inconsistent about what to name case classes that provide parameters to modules. Settled on calling them [ModuleName]Params to distinguish them from config.Parameters and config.Config. So far applied mostly only to case classes defined within rocket and tile. * Defined RocketTileParams: A nested case class containing case classes for all the components of a tile (L1 caches and core). Allows all such parameters to vary per-tile. * Defined RocketCoreParams: All the parameters that can be varied per-core. * Defined L1CacheParams: A trait defining the parameters common to L1 caches, made concrete in different derived case classes. * Defined RocketTilesKey: A sequence of RocketTileParams, one for every tile to be created. * Provided HeterogeneousDualCoreConfig: An example of making a heterogeneous chip with two cores, one big and one little. * Changes to legacy code: ReplacementPolicy moved to package util. L1Metadata moved to package tile. Legacy L2 cache agent removed because it can no longer share the metadata array implementation with the L1. Legacy GroundTests on life support. Additional changes that got rolled in along the way: * rocket: Fix critical path through BTB for I$ index bits > pgIdxBits * coreplex: tiles connected via :=* * groundtest: updated to use TileParams * tilelink: cache cork requirements are relaxed to allow more cacheless masters
This commit is contained in:
Henry Cook
GitHub
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// See LICENSE.Berkeley for license details.
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// See LICENSE.SiFive for license details.
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package uncore.util
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import Chisel._
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import config.{Parameters, Field}
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import rocket.PAddrBits
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import util.ParameterizedBundle
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import uncore.constants._
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case class CacheConfig(
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nSets: Int,
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nWays: Int,
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rowBits: Int,
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nTLBEntries: Int,
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cacheIdBits: Int,
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splitMetadata: Boolean)
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case class CacheName(id: String) extends Field[CacheConfig]
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case object CacheName extends Field[CacheName]
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case object Replacer extends Field[() => ReplacementPolicy]
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case object L2Replacer extends Field[() => SeqReplacementPolicy]
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case object NPrimaryMisses extends Field[Int]
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case object NSecondaryMisses extends Field[Int]
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case object CacheBlockBytes extends Field[Int]
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case object ECCCode extends Field[Option[Code]]
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trait HasCacheParameters {
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implicit val p: Parameters
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val cacheConfig = p(p(CacheName))
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val nSets = cacheConfig.nSets
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val blockOffBits = log2Up(p(CacheBlockBytes))
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val cacheIdBits = cacheConfig.cacheIdBits
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val idxBits = log2Up(cacheConfig.nSets)
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val untagBits = blockOffBits + cacheIdBits + idxBits
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val tagBits = p(PAddrBits) - untagBits
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val nWays = cacheConfig.nWays
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val wayBits = log2Up(nWays)
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val isDM = nWays == 1
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val rowBits = cacheConfig.rowBits
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val rowBytes = rowBits/8
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val rowOffBits = log2Up(rowBytes)
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val code = p(ECCCode).getOrElse(new IdentityCode)
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val hasSplitMetadata = cacheConfig.splitMetadata
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}
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abstract class CacheModule(implicit val p: Parameters) extends Module
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with HasCacheParameters
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abstract class CacheBundle(implicit val p: Parameters) extends ParameterizedBundle()(p)
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with HasCacheParameters
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abstract class ReplacementPolicy {
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def way: UInt
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def miss: Unit
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def hit: Unit
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}
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class RandomReplacement(ways: Int) extends ReplacementPolicy {
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private val replace = Wire(Bool())
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replace := Bool(false)
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val lfsr = LFSR16(replace)
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def way = if(ways == 1) UInt(0) else lfsr(log2Up(ways)-1,0)
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def miss = replace := Bool(true)
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def hit = {}
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}
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abstract class SeqReplacementPolicy {
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def access(set: UInt): Unit
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def update(valid: Bool, hit: Bool, set: UInt, way: UInt): Unit
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def way: UInt
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}
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class SeqRandom(n_ways: Int) extends SeqReplacementPolicy {
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val logic = new RandomReplacement(n_ways)
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def access(set: UInt) = { }
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def update(valid: Bool, hit: Bool, set: UInt, way: UInt) = {
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when (valid && !hit) { logic.miss }
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}
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def way = logic.way
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}
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class PseudoLRU(n: Int)
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{
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require(isPow2(n))
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val state_reg = Reg(Bits(width = n))
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def access(way: UInt) {
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state_reg := get_next_state(state_reg,way)
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}
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def get_next_state(state: UInt, way: UInt) = {
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var next_state = state
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var idx = UInt(1,1)
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for (i <- log2Up(n)-1 to 0 by -1) {
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val bit = way(i)
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next_state = next_state.bitSet(idx, !bit)
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idx = Cat(idx, bit)
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}
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next_state
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}
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def replace = get_replace_way(state_reg)
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def get_replace_way(state: Bits) = {
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var idx = UInt(1,1)
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for (i <- 0 until log2Up(n))
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idx = Cat(idx, state(idx))
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idx(log2Up(n)-1,0)
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}
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}
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class SeqPLRU(n_sets: Int, n_ways: Int) extends SeqReplacementPolicy {
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val state = SeqMem(n_sets, Bits(width = n_ways-1))
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val logic = new PseudoLRU(n_ways)
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val current_state = Wire(Bits())
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val plru_way = logic.get_replace_way(current_state)
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val next_state = Wire(Bits())
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def access(set: UInt) = {
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current_state := Cat(state.read(set), Bits(0, width = 1))
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}
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def update(valid: Bool, hit: Bool, set: UInt, way: UInt) = {
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val update_way = Mux(hit, way, plru_way)
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next_state := logic.get_next_state(current_state, update_way)
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when (valid) { state.write(set, next_state(n_ways-1,1)) }
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}
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def way = plru_way
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}
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abstract class Metadata(implicit p: Parameters) extends CacheBundle()(p) {
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val tag = Bits(width = tagBits)
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}
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class MetaReadReq(implicit p: Parameters) extends CacheBundle()(p) {
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val idx = Bits(width = idxBits)
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val way_en = Bits(width = nWays)
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}
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class MetaWriteReq[T <: Metadata](gen: T)(implicit p: Parameters) extends MetaReadReq()(p) {
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val data = gen.cloneType
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override def cloneType = new MetaWriteReq(gen)(p).asInstanceOf[this.type]
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}
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class MetadataArray[T <: Metadata](onReset: () => T)(implicit p: Parameters) extends CacheModule()(p) {
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val rstVal = onReset()
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val io = new Bundle {
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val read = Decoupled(new MetaReadReq).flip
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val write = Decoupled(new MetaWriteReq(rstVal)).flip
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val resp = Vec(nWays, rstVal.cloneType).asOutput
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}
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val rst_cnt = Reg(init=UInt(0, log2Up(nSets+1)))
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val rst = rst_cnt < UInt(nSets)
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val waddr = Mux(rst, rst_cnt, io.write.bits.idx)
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val wdata = Mux(rst, rstVal, io.write.bits.data).asUInt
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val wmask = Mux(rst || Bool(nWays == 1), SInt(-1), io.write.bits.way_en.asSInt).toBools
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val rmask = Mux(rst || Bool(nWays == 1), SInt(-1), io.read.bits.way_en.asSInt).toBools
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when (rst) { rst_cnt := rst_cnt+UInt(1) }
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val metabits = rstVal.getWidth
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if (hasSplitMetadata) {
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val tag_arrs = List.fill(nWays){ SeqMem(nSets, UInt(width = metabits)) }
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val tag_readout = Wire(Vec(nWays,rstVal.cloneType))
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(0 until nWays).foreach { (i) =>
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when (rst || (io.write.valid && wmask(i))) {
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tag_arrs(i).write(waddr, wdata)
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}
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io.resp(i) := rstVal.fromBits(tag_arrs(i).read(io.read.bits.idx, io.read.valid && rmask(i)))
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}
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} else {
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val tag_arr = SeqMem(nSets, Vec(nWays, UInt(width = metabits)))
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when (rst || io.write.valid) {
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tag_arr.write(waddr, Vec.fill(nWays)(wdata), wmask)
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}
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io.resp := tag_arr.read(io.read.bits.idx, io.read.valid).map(rstVal.fromBits(_))
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}
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io.read.ready := !rst && !io.write.valid // so really this could be a 6T RAM
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io.write.ready := !rst
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}
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