Heterogeneous Tiles (#550)

Fundamental new features:

* Added tile package: This package is intended to hold components re-usable across different types of tile. Will be the future location of TL2-RoCC accelerators and new diplomatic versions of intra-tile interfaces.
* Adopted [ModuleName]Params convention: Code base was very inconsistent about what to name case classes that provide parameters to modules. Settled on calling them [ModuleName]Params to distinguish them from config.Parameters and config.Config. So far applied mostly only to case classes defined within rocket and tile.
* Defined RocketTileParams: A nested case class containing case classes for all the components of a tile (L1 caches and core). Allows all such parameters to vary per-tile.
* Defined RocketCoreParams: All the parameters that can be varied per-core.
* Defined L1CacheParams: A trait defining the parameters common to L1 caches, made concrete in different derived case classes.
* Defined RocketTilesKey: A sequence of RocketTileParams, one for every tile to be created.
* Provided HeterogeneousDualCoreConfig: An example of making a heterogeneous chip with two cores, one big and one little.
* Changes to legacy code: ReplacementPolicy moved to package util. L1Metadata moved to package tile. Legacy L2 cache agent removed because it can no longer share the metadata array implementation with the L1. Legacy GroundTests on life support.

Additional changes that got rolled in along the way:

* rocket: 	Fix critical path through BTB for I$ index bits > pgIdxBits
* coreplex: tiles connected via :=*
* groundtest: updated to use TileParams
* tilelink: cache cork requirements are relaxed to allow more cacheless masters

src/main/scala/uncore/devices/Debug.scala

@@ -6,6 +6,7 @@ import Chisel._
 import junctions._
 import util._
 import regmapper._
+import tile.XLen
 import uncore.tilelink2._
 import config._
 
@@ -848,7 +849,7 @@ trait DebugModule extends Module with HasDebugModuleParameters with HasRegMap {
   */
 
 class TLDebugModule(address: BigInt = 0)(implicit p: Parameters)
-  extends TLRegisterRouter(address, beatBytes=p(rocket.XLen)/8, executable=true)(
+  extends TLRegisterRouter(address, beatBytes=p(XLen)/8, executable=true)(
   new TLRegBundle((), _ )    with DebugModuleBundle)(
   new TLRegModule((), _, _)  with DebugModule)
 

src/main/scala/uncore/devices/Plic.scala

@@ -11,6 +11,7 @@ import regmapper._
 import uncore.tilelink2._
 import config._
 import scala.math.min
+import tile.XLen
 
 class GatewayPLICIO extends Bundle {
   val valid = Bool(OUTPUT)
@@ -59,7 +60,7 @@ class TLPLIC(supervisor: Boolean, maxPriorities: Int, address: BigInt = 0xC00000
 
   val node = TLRegisterNode(
     address   = AddressSet(address, PLICConsts.size-1),
-    beatBytes = p(rocket.XLen)/8,
+    beatBytes = p(XLen)/8,
     undefZero = false)
 
   val intnode = IntNexusNode(

src/main/scala/uncore/devices/Prci.scala

@@ -12,6 +12,7 @@ import uncore.util._
 import util._
 import scala.math.{min,max}
 import config._
+import tile.XLen
 
 /** Number of tiles */
 case object NTiles extends Field[Int]
@@ -83,7 +84,7 @@ trait CoreplexLocalInterrupterModule extends Module with HasRegMap with MixCorep
 /** Power, Reset, Clock, Interrupt */
 // Magic TL2 Incantation to create a TL2 Slave
 class CoreplexLocalInterrupter(address: BigInt = 0x02000000)(implicit p: Parameters)
-  extends TLRegisterRouter(address, size = ClintConsts.size, beatBytes = p(rocket.XLen)/8, undefZero = true)(
+  extends TLRegisterRouter(address, size = ClintConsts.size, beatBytes = p(XLen)/8, undefZero = true)(
   new TLRegBundle((), _)    with CoreplexLocalInterrupterBundle)(
   new TLRegModule((), _, _) with CoreplexLocalInterrupterModule)
 {