Heterogeneous Tiles (#550)

Fundamental new features:

* Added tile package: This package is intended to hold components re-usable across different types of tile. Will be the future location of TL2-RoCC accelerators and new diplomatic versions of intra-tile interfaces.
* Adopted [ModuleName]Params convention: Code base was very inconsistent about what to name case classes that provide parameters to modules. Settled on calling them [ModuleName]Params to distinguish them from config.Parameters and config.Config. So far applied mostly only to case classes defined within rocket and tile.
* Defined RocketTileParams: A nested case class containing case classes for all the components of a tile (L1 caches and core). Allows all such parameters to vary per-tile.
* Defined RocketCoreParams: All the parameters that can be varied per-core.
* Defined L1CacheParams: A trait defining the parameters common to L1 caches, made concrete in different derived case classes.
* Defined RocketTilesKey: A sequence of RocketTileParams, one for every tile to be created.
* Provided HeterogeneousDualCoreConfig: An example of making a heterogeneous chip with two cores, one big and one little.
* Changes to legacy code: ReplacementPolicy moved to package util. L1Metadata moved to package tile. Legacy L2 cache agent removed because it can no longer share the metadata array implementation with the L1. Legacy GroundTests on life support.

Additional changes that got rolled in along the way:

* rocket: 	Fix critical path through BTB for I$ index bits > pgIdxBits
* coreplex: tiles connected via :=*
* groundtest: updated to use TileParams
* tilelink: cache cork requirements are relaxed to allow more cacheless masters

src/main/scala/rocketchip/Configs.scala

@@ -38,33 +38,21 @@ class BasePlatformConfig extends Config((site, here, up) => {
   case RTCPeriod => 100 // gives 10 MHz RTC assuming 1 GHz uncore clock
 })
 
+/** Actual elaboratable target Configs */
+
 class BaseConfig extends Config(new BaseCoreplexConfig ++ new BasePlatformConfig)
-class DefaultConfig extends Config(new WithBlockingL1 ++ new BaseConfig)
+class DefaultConfig extends Config(new WithBlockingL1 ++ new WithNBigCores(1) ++ new BaseConfig)
 
-class DefaultL2Config extends Config(new WithL2Cache ++ new BaseConfig)
+class DefaultL2Config extends Config(new WithL2Cache ++ new WithNBigCores(1) ++ new BaseConfig)
 class DefaultBufferlessConfig extends Config(
-  new WithBufferlessBroadcastHub ++ new BaseConfig)
-
-class FPGAConfig extends Config ((site, here, up) => {
-  case NAcquireTransactors => 4
-})
+  new WithBufferlessBroadcastHub ++ new WithNBigCores(1) ++ new BaseConfig)
 
+class FPGAConfig extends Config(Parameters.empty)
 class DefaultFPGAConfig extends Config(new FPGAConfig ++ new BaseConfig)
 class DefaultL2FPGAConfig extends Config(
   new WithL2Capacity(64) ++ new WithL2Cache ++ new DefaultFPGAConfig)
 
-class WithNMemoryChannels(n: Int) extends Config((site, here, up) => {
-  case BankedL2Config => up(BankedL2Config, site).copy(nMemoryChannels = n)
-})
-
-class WithExtMemSize(n: Long) extends Config((site, here, up) => {
-  case ExtMem => up(ExtMem, site).copy(size = n)
-})
-
-class WithScratchpads extends Config(new WithNMemoryChannels(0) ++ new WithDataScratchpad(16384))
-
-class DefaultFPGASmallConfig extends Config(new WithSmallCores ++ new DefaultFPGAConfig)
-class DefaultSmallConfig extends Config(new WithSmallCores ++ new BaseConfig)
+class DefaultSmallConfig extends Config(new WithNSmallCores(1) ++ new BaseConfig)
 class DefaultRV32Config extends Config(new WithRV32 ++ new DefaultConfig)
 
 class DualBankConfig extends Config(
@@ -83,12 +71,7 @@ class DualChannelDualBankL2Config extends Config(
   new WithNMemoryChannels(2) ++ new WithNBanksPerMemChannel(2) ++
   new WithL2Cache ++ new BaseConfig)
 
-class RoccExampleConfig extends Config(new WithRoccExample ++ new BaseConfig)
-
-class WithEdgeDataBits(dataBits: Int) extends Config((site, here, up) => {
-  case ExtMem => up(ExtMem, site).copy(beatBytes = dataBits/8)
-  case ZeroConfig => up(ZeroConfig, site).copy(beatBytes = dataBits/8)
-})
+class RoccExampleConfig extends Config(new WithRoccExample ++ new DefaultConfig)
 
 class Edge128BitConfig extends Config(
   new WithEdgeDataBits(128) ++ new BaseConfig)
@@ -107,12 +90,22 @@ class OctoChannelBenchmarkConfig extends Config(new WithNMemoryChannels(8) ++ ne
 class EightChannelConfig extends Config(new WithNMemoryChannels(8) ++ new BaseConfig)
 
 class DualCoreConfig extends Config(
-  new WithNCores(2) ++ new WithL2Cache ++ new BaseConfig)
+  new WithNBigCores(2) ++ new WithL2Cache ++ new BaseConfig)
+class HeterogeneousDualCoreConfig extends Config(
+  new WithNSmallCores(1) ++ new WithNBigCores(1) ++ new WithL2Cache ++ new BaseConfig)
 
 class TinyConfig extends Config(
-  new WithScratchpads ++
-  new WithSmallCores ++ new WithRV32 ++
-  new WithStatelessBridge ++ new BaseConfig)
+  new WithScratchpad ++
+  new WithRV32 ++
+  new WithStatelessBridge ++
+  new WithNSmallCores(1) ++ new BaseConfig)
+
+/* Composable partial function Configs to set individual parameters */
+
+class WithEdgeDataBits(dataBits: Int) extends Config((site, here, up) => {
+  case ExtMem => up(ExtMem, site).copy(beatBytes = dataBits/8)
+  case ZeroConfig => up(ZeroConfig, site).copy(beatBytes = dataBits/8)
+})
 
 class WithJtagDTM extends Config ((site, here, up) => {
   case IncludeJtagDTM => true
@@ -134,10 +127,18 @@ class WithNExtTopInterrupts(nExtInts: Int) extends Config((site, here, up) => {
   case NExtTopInterrupts => nExtInts
 })
 
-class WithNBreakpoints(hwbp: Int) extends Config ((site, here, up) => {
-  case NBreakpoints => hwbp
-})
-
 class WithRTCPeriod(nCycles: Int) extends Config((site, here, up) => {
   case RTCPeriod => nCycles
 })
+
+class WithNMemoryChannels(n: Int) extends Config((site, here, up) => {
+  case BankedL2Config => up(BankedL2Config, site).copy(nMemoryChannels = n)
+})
+
+class WithExtMemSize(n: Long) extends Config((site, here, up) => {
+  case ExtMem => up(ExtMem, site).copy(size = n)
+})
+
+class WithScratchpad extends Config(new WithNMemoryChannels(0) ++ new WithDataScratchpad(16384))
+
+class DefaultFPGASmallConfig extends Config(new WithNSmallCores(1) ++ new DefaultFPGAConfig)

src/main/scala/rocketchip/Generator.scala

@@ -2,7 +2,9 @@
 
 package rocketchip
 
-import rocket.{XLen, UseVM, UseAtomics, UseCompressed, FPUKey}
+import tile.XLen
+import coreplex.RocketTilesKey
+
 import scala.collection.mutable.LinkedHashSet
 
 /** A Generator for platforms containing Rocket Coreplexes */
@@ -47,9 +49,11 @@ object Generator extends util.GeneratorApp {
   override def addTestSuites {
     import DefaultTestSuites._
     val xlen = params(XLen)
-    val vm = params(UseVM)
+    // TODO: for now only generate tests for the first core in the first coreplex
+    val coreParams = params(RocketTilesKey).head.core
+    val vm = coreParams.useVM
     val env = if (vm) List("p","v") else List("p")
-    params(FPUKey) foreach { case cfg =>
+    coreParams.fpu foreach { case cfg =>
       if (xlen == 32) {
         TestGeneration.addSuites(env.map(rv32ufNoDiv))
       } else {
@@ -62,8 +66,8 @@ object Generator extends util.GeneratorApp {
         }
       }
     }
-    if (params(UseAtomics))    TestGeneration.addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))
-    if (params(UseCompressed)) TestGeneration.addSuites(env.map(if (xlen == 64) rv64uc else rv32uc))
+    if (coreParams.useAtomics)    TestGeneration.addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))
+    if (coreParams.useCompressed) TestGeneration.addSuites(env.map(if (xlen == 64) rv64uc else rv32uc))
     val (rvi, rvu) =
       if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u)
       else            ((if (vm) rv32i else rv32pi), rv32u)

src/main/scala/rocketchip/Periphery.scala

@@ -4,20 +4,16 @@ package rocketchip
 
 import Chisel._
 import config._
-import junctions._
-import junctions.NastiConstants._
+import coreplex._
 import diplomacy._
-import uncore.tilelink._
+import tile.XLen
 import uncore.tilelink2._
 import uncore.axi4._
 import uncore.converters._
 import uncore.devices._
-import uncore.agents._
 import uncore.util._
 import util._
-import rocket.XLen
 import scala.math.max
-import coreplex._
 
 /** Specifies the size of external memory */
 case class MasterConfig(base: Long, size: Long, beatBytes: Int, idBits: Int)

src/main/scala/rocketchip/Utils.scala

@@ -6,7 +6,7 @@ import config._
 import junctions._
 import diplomacy._
 import uncore.devices._
-import rocket._
+import tile.XLen
 import coreplex._
 import uncore.tilelink2._
 import util._
@@ -59,14 +59,15 @@ object GenerateConfigString {
     res append plic.globalConfigString
     res append clint.globalConfigString
     res append  "core {\n"
-    for (i <- 0 until c.nTiles) { // TODO heterogeneous tiles
+    c.tilesParams.zipWithIndex.map { case(t, i) => 
       val isa = {
-        val m = if (p(MulDivKey).nonEmpty) "m" else ""
-        val a = if (p(UseAtomics)) "a" else ""
-        val f = if (p(FPUKey).nonEmpty) "f" else ""
-        val d = if (p(FPUKey).nonEmpty && p(XLen) > 32) "d" else ""
-        val s = if (c.hasSupervisor) "s" else ""
-        s"rv${p(XLen)}i$m$a$f$d$s"
+        val m = if (t.core.mulDiv.nonEmpty) "m" else ""
+        val a = if (t.core.useAtomics) "a" else ""
+        val f = if (t.core.fpu.nonEmpty) "f" else ""
+        val d = if (t.core.fpu.nonEmpty && p(XLen) > 32) "d" else ""
+        val c = if (t.core.useCompressed) "c" else ""
+        val s = if (t.core.useVM) "s" else ""
+        s"rv${p(XLen)}i$m$a$f$d$c$s"
       }
       res append s"  $i {\n"
       res append  "    0 {\n"